-
After some time, I have returned to using amforth, and I have found the reason why the simulation fails.
The amforth erases the flash page only when the write operation changes any '0' bit to '1'.
It works perfectly in the real AVR, but fails in the VMLAB, so it seems to be a bug in the VMLAB.
If someone wants to simulate amforth with the current version of the VMLAB, it is necessary to...
2009-09-14 18:40:36 UTC in amforth: Forth for AVR ATmega
-
I have uploaded the GHW file (in the gzipped form), which is generated by the GHDL from the sources included in the demo.zip file.
2009-06-21 22:36:24 UTC in gtkwave
-
The new "sfixed" and "fixed" types, containing bits with positive and negative indices, are displayes incorrectly.
The attached zip file contains the simple project ilustrating the problem.
To run it, you should first run the "comp.sh" to compile the fixed point packages, and then "make" to compile and
run the simulation.
The signal "out_smp" is displayed with positive indices as a group...
2009-06-13 10:00:34 UTC in gtkwave
-
Hi,
I have just succeeded to access the Virtual JTAG in the Altera FPGA via urJTAG+Python code.
It is very simple code, which just allows to use JTAG to blink a few LEDs, but it may be easily extended to more serious applications.
It performs the enumeration of the SDL nodes, and then access the DR register connected to the selected node.
The code may be found here...
2009-05-27 19:10:29 UTC in Universal JTAG library, server and tools
-
OK. I've verified, that two instructions with the same CODE and different REGISTERs are accepted by the urJTAG:
jtag> REGISTER UR 18
jtag> REGISTER URL 100
jtag> INSTRUCTION USER1 000010 UR
jtag> INSTRUCTION USER1L 000010 URL
jtag> INSTRUCTION USER1
jtag> shift dr :: dr
000000000000000000
jtag> INSTRUCTION USER1L
jtag> shift dr :: dr...
2009-05-20 15:44:53 UTC in Universal JTAG library, server and tools
-
Hi,
I need to access the JTAG chain via the Xilinx XPCU cable with urJTAG from Python script.
Currently I have developed simple code allowing to do it (published at http://groups.google.pl/group/alt.sources/browse_thread/thread/603ff14bdf020776# ). It uses urJTAG interactively, via urJTAG shell and Python pexpect package. Unfortunately this method is awfully slow.
(Now I have also the...
2009-05-20 13:40:04 UTC in Universal JTAG library, server and tools
-
I have created simple code allowing me to use the urJTAG from the Python code.
It was tailored for controlling of the Xilinx FPGAs vie the BSCAN_SPARTAN3 component.
I've checked it with the embedded USB cable included in SPARTAN-3E Starter Kit, but it
should also work with other cables supported by urJTAG.
Unfortunately this code runs urJTAG interactively via Python's "pexpect" module, and...
2009-05-17 20:25:14 UTC in Universal JTAG library, server and tools
-
I have seen, that someone has proposed building of Python interpreter into urJTAG: https://sourceforge.net/tracker/index.php?func=detail&aid=1824424&group_id=193266&atid=944728
However I think, that also the opposite - calling the urJTAG functions from the Python could be nice.
2009-05-17 14:37:04 UTC in Universal JTAG library, server and tools
-
OK. I've got it. The "marker" requires not only set-order, but also set-current.
In fact I really don't know, why I haven't noticed, that the line causing problems
contains set-current, not set-current :-(.
And additionally the same topic was discussed here just two days before: http://sourceforge.net/mailarchive/message.php?msg_name=49F73F5D.2060504%40nassur.net
The resolution is very...
2009-05-10 13:35:43 UTC in amforth: Forth for AVR ATmega
-
I tried to generate simple parametrized IIR filter using MyHDL. The resulting code is as follows:
def iir(din, dout, nbits, acoeffs, bcoeffs, clk, n_rst):
del_len = max(len(acoeffs),len(bcoeffs))
del_line = [ Signal(intbv(0,min=din.min,max=din.max)) for i in range(del_len-1)]
@always(clk.posedge, n_rst.negedge)
def logic():
if n_rst==0:
for i in range(0,del_len):
2009-05-02 22:26:14 UTC in MyHDL
