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Synthesis is not supported in the 0.9 release series. It has been hard to keep it up given all the other changes in the simulator, and the demand has been low. Users typically use Icarus Verilog for simulation and development, then use the free vendor tools to do synthesis, P&R.
2009-11-07 15:04:52 UTC in Icarus Verilog
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Synthesis is not supported in the 0.9 release series. It has been hard to keep it up given all the other changes in the simulator, and the demand has been low. Users typically use Icarus Verilog for simulation and development, then use the free vendor tools to do synthesis, P&R.
2009-11-07 15:04:03 UTC in Icarus Verilog
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It's generated by the autoconf.sh script. See the developer documentation at this link:
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2009-11-04 15:49:47 UTC in Icarus Verilog
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Applied to git master.
2009-11-03 22:48:09 UTC in Icarus Verilog
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Applied to git v0_9-branch.
2009-11-03 22:48:09 UTC in Icarus Verilog
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First off, the commands that you are missing are part of the WebPACK or Foundation software from Xilinx, and are not part of Icarus Verilog. To target Xilinx FPGA devices for synthesis, you need the Xilinx software.
Second, while Icarus Verilog is great for simulating designs intended for FPGA implementation, you would be better off synthesizing your FPGA design with the vendor tools. The...
2009-11-02 17:27:47 UTC in Icarus Verilog
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Applied to git v0_9-branch.
2009-11-01 19:12:14 UTC in Icarus Verilog
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Applied to git master.
2009-11-01 19:08:26 UTC in Icarus Verilog
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Applied to git v0_9-branch.
2009-11-01 19:03:03 UTC in Icarus Verilog
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Applied to git v0_9-branch.
2009-11-01 19:01:22 UTC in Icarus Verilog
