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Hi
Please add support for Codefolding for vhdl if-else, for, while statements (In that preference order).
Thank you.
2009-11-17 11:19:21 UTC in Eclipse Verilog editor
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Hi
I am using veditorv 0.7.0, eclipse 3.5.1
I have a testbench with all the verif tests in. (Reason for large file)
As soon as the vhdl file gets larger than +-500k, "Outline" stops working. (Hierarchy aswell)
I made a very simple test vhdl file. Same thing, >500k "Outline" stop working.
Is there a setting to inrease this file size limit?
Thanks.
2009-11-13 11:22:57 UTC in Eclipse Verilog editor
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Is there a way to enable codefolding for VHDL
if, for, while statements?.
2009-11-13 10:51:29 UTC in Eclipse Verilog editor
