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Hi Trevor
I have a failure where an extra character appears during annotation. An input line like
assign QB = ham[AddressB_Q];
(with a leading tab) results in an output line like
assign QB = h \covered$X23_19_19_d001b
where the 'h' is a syntax error. I'll mail you the testcase file.
Cheers
Ed.
2009-09-21 11:28:14 UTC in Covered
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Hi Trevor
is there anything I can do to help you with this?
Cheers
Ed.
2009-09-14 15:23:34 UTC in Covered
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Hi Trevor
Having tweaked the sources to workaround the problem with loops initialising memories, I'm seeing an assertion at the time of scoring the vcd file.
I have been able to cut down the vcd file to mention only a single signal, and I've got obfuscated versions of the vcd and the cdd, but I can't readily create a subset of the cdd file.
Is there anything useful I can do in the...
2009-08-10 14:46:32 UTC in Covered
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Hi Trevor
as discussed, it turns out I'm seeing valgrind errors, and the verilator error is very sensitive to the exact text in the original source, so I'm thinking this is a low level bug. I've sent you a private testcase.
cheers
Ed.
2009-08-06 10:18:52 UTC in Covered
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Hi Trevor
there is a problem when annotating a design with loops: I'm seeing
%Error-BLKLOOPINIT: ../../aos_x/src/aos_x_m.v:1405: Unsupported:
Delayed assignment to array inside for loops (non-delayed is ok - see
docs)
when the following snippet
387: for ( a1043 =`aos_x_hi ; a1043 >0; a1043 = a1043 -1)
388: begin
389: a1023 [ a1043 ]
2009-08-04 18:13:18 UTC in Covered
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Hi Trevor
This is just a warning from verilator, but I expect you'll want to get everything warning-free.
$ verilator -cc "covered/verilog/test-unsized.v"
%Warning-WIDTHCONCAT: covered/verilog/test-unsized.v:49: Unsized numbers/parameters not allowed in concatenations.
where the instrumented code looks like
\covered$X26_36_36_2b003d = {0, a1005[1:0]};
Please find the...
2009-08-03 18:40:56 UTC in Covered
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Hi Trevor
I think this is a distinct code generation issue. The generated code looks like this:
65: if ( \covered$X1e_22_22_f0020 ) \covered$R22_22_110020$a1001$a2003.u$0 = ((1)-((~a1005)-(0)))*(2);
66: begin \covered$L23_23_80014$a2003.u$0 = 1'b1;
67: a1006 = 5'd16; end
68: else begin \covered$L25_25_80014$a2003.u$0 = 1'b1;
and I think the target of the if is not...
2009-08-03 17:37:06 UTC in Covered
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Hi Trevor
I see that in my original design, the output code is slightly more mangled than it is for the testcase. There is an extra "0)" stuck in there, and only one of the three function calls has survived:
assign
a1013 = a1116 ,
a1014 = \covered$X3a_1166_1166_250064 , wire...
\covered$X3a_1167_1167_250064 0)a1015 = \covered$X3a_1168_1168_250064 , wire...
a1016 =...
2009-08-03 15:39:23 UTC in Covered
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Hi Trevor
with the testcase below I get an 'end' embedded in a case label in the instrumented verilog, like this:
5'd0: begin
if ( a1006 ) begin
a1004 = 1'b1; end
5 end 'd1: begin
Please see below
thanks
Ed
module a1000 (
input a1001 ,
input a1002
);
always @*
begin : a1003
a1004 = a1005 ;
case ( a1005 )
5'd0:
if ( a1006 )
a1004 = 1'b1;
5'd1:
begin
case (1'b1...
2009-08-03 15:21:48 UTC in Covered
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Hi Trevor
I'm using the latest dev snapshot. I find a wire declaration misplaced, like this:
assign
a1013 = a1116 ,
a1014 = \covered$X3a_28_28_80019 ,wire [(32)-1:0] \covered$r28_28_100018$a1043 = ((0)-(0))*(24);
\covered$X3a_29_29_80019 a1015 = \covered$X3a_30_30_80019 ,wire [(32)-1:0] \covered$r29_29_100018$a1043 = ((1)-(0))*(24);
Please find the testcase below.
Thanks...
2009-08-03 14:54:29 UTC in Covered
