#933 Simulation hangs with no reason

Cary R. — Tue, 18 Jun 2013 18:45:21 -0000

status: open --> closed-invalid

#933 Simulation hangs with no reason

Cary R. — Fri, 14 Jun 2013 20:09:08 -0000

Yes, the wires/port which can act like a continuous assignment change the glitch dynamic.

#32 ifnone compiler error (no support for Cadence syntax)

Cary R. — Fri, 14 Jun 2013 20:03:55 -0000

Just so you know, this functionality will never be implemented in the V0.9 branch and it is also not part of the Verilog standard (it is a Cadence addition). If we don't have to implement/worry about the SDF back annotation then this would be easier to add. Enhancing SDF back annotation to work correctly for this and other constructs requires a major rework of the run time expression code. Since Icarus has known issues with specify blocks ans SDF support this specific report has been a low priority. If you can live without SDF support we may be able to add this functionality in a more timely manner.

#932 string type as an input into a task

Cary R. — Fri, 14 Jun 2013 16:53:40 -0000

Martin,

Are you going to also fix the $fopen() bug? I'm guessing there could be a number of other system tasks/functions that should take a string that currently fail since the string type is a fairly new addition to Icarus.

#933 Simulation hangs with no reason

Cary R. — Fri, 14 Jun 2013 16:50:51 -0000

#43 support for SystemVerilog "package"

Cary R. — Tue, 14 May 2013 22:33:55 -0000

status: open --> closed
assigned_to: Stephen Williams
Group: --> devel_(Next_Release)

#42 support for SystemVerilog "end labels"

Cary R. — Tue, 14 May 2013 22:27:37 -0000

status: open --> closed
assigned_to: Cary R.
Group: --> devel_(Next_Release)

#930 Icarus 0.9.6 syntax error on synthesis attribute

Cary R. — Tue, 07 May 2013 01:45:26 -0000

Group: v0.9 --> devel

#929 Semantics for ==/!= and X

Cary R. — Wed, 01 May 2013 02:45:58 -0000

status: open --> closed-invalid
Group: devel --> v0.9

#928 No support for passing arrays (SystemVerilog)

Cary R. — Thu, 18 Apr 2013 02:05:25 -0000

summary: 2D array fails as input --> No support for passing arrays (SystemVerilog)
Group: v0.9 --> devel

Recent posts by Cary R.

#933 Simulation hangs with no reason

#933 Simulation hangs with no reason

#32 ifnone compiler error (no support for Cadence syntax)

#932 string type as an input into a task

#933 Simulation hangs with no reason

#43 support for SystemVerilog "package"

#42 support for SystemVerilog "end labels"

#930 Icarus 0.9.6 syntax error on synthesis attribute

#929 Semantics for ==/!= and X

#928 No support for passing arrays (SystemVerilog)