Signs - VHDL Hardware Developement

Error message:
Parser Error: module keyword expected.

The source code begins with comments e.g.

// timescale

then followed by a `timescale directive:

`timescale
Which is the line that causes the error.

then some more comments and `-directives.
and finally:

module modname (

etc.

The verilog source is known good and working without error in simulation
and synthesis.

So, this Error message is annoying. Maybe caused by the underlying JavaCC?
(using the recommended JavaCC from
http://pagesperso-orange.fr/eclipse_javacc/ )