Icarus Verilog

Tracker: Bugs

5 Exactly equal bug or initialization race - ID: 2415227

Last Update: Comment added ( theosib )

Details:

This code produces an incorrect value on variable 'a':

module test;

reg b;
wire a;
assign a = b===1 ? 1'b0 : 1'bz;

initial begin
$dumpfile( "test.vcd" );
$dumpvars;
#100;
end

endmodule

Since b is not exactly equal to 1, the test should evaluate to false, and
so 'a' should be assigned a value of 'z'. Instead, it stays 'x'.

Submitted:

Timothy Miller ( theosib ) - 2008-12-10 23:39

Priority:

Status:

Closed

Resolution:

Works For Me

Assigned:

Nobody/Anonymous

Category:

Verilog compiler bug

Group:

devel

Visibility:

Public

Comments ( 3 )

Date: 2008-12-17 17:45 Sender: theosib I'm an idiot. Sorry about this. When I cleaned up the build problems I was having, the latest version fixed the bug. Thank you for your patience!
Date: 2008-12-17 17:39 Sender: theosib Please reopen this bug. I checked out the latest git version, compiled it, and installed it, and when I run this, I still get solid X for a, when I should get Z.
Date: 2008-12-11 03:31 Sender: stevewilliams It works properly for me. Since you don't say what version you are using, I'll assume that it is already fixed in git.

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Changes ( 7 )

Field	Old Value	Date	By
status_id	Open	2008-12-17 17:45	theosib
close_date	-	2008-12-17 17:45	theosib
status_id	Closed	2008-12-17 17:39	theosib
close_date	2008-12-11 03:31	2008-12-17 17:39	theosib
resolution_id	None	2008-12-11 03:31	stevewilliams
close_date	-	2008-12-11 03:31	stevewilliams
status_id	Open	2008-12-11 03:31	stevewilliams

Icarus Verilog

Tracker: Bugs

Comments ( 3 )

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Changes ( 7 )

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