When format VHDL codes using "Ctrl+Shift+F" or "Edit->format" from menu,
some code is mal-formated. For example,
trn_td : out std_logic_vector(63 downto 0);
will be formated to:
trn_td : o u t std_logic_vector(63 downto 0);
(attetion to the blank in word "out")
and quite a lot other wired mal-formated bahavior existed.
Version: 0.6.0
Eclipse Version: 3.2.2
submitter email: wl.pkucs at gmail.com
Nobody/Anonymous ( nobody ) - 2007-11-06 07:43
5
Closed
None
Nobody/Anonymous
editor
None
Public
|
Date: 2009-05-12 13:29 Tested successfully with version 0.6.3. Closing bug. |
|
Date: 2007-12-12 17:05 Logged In: NO |
| Field | Old Value | Date | By |
|---|---|---|---|
| status_id | Open | 2009-05-12 13:29 | simonmartineau |
| allow_comments | 1 | 2009-05-12 13:29 | simonmartineau |
| close_date | - | 2009-05-12 13:29 | simonmartineau |