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SystemVerilog FrameWorks(TM)	3,095	98.90%	2009-05-16	2009-07-20	1,132
This is a collection of tools and a code library to assist engineers who are developing SystemVerilog based verification environments. Components include utility libraries, scoreboard and shutdown manager implementation, register tool, etc. Topic: Electronic Design Automation (EDA), Templates, Object Oriented, Modeling, Libraries, Frameworks Programming Language: VHDL/Verilog, C++ Operating System: WinXP, Linux License: Apache License V2.0 Intended Audience: Telecommunications Industry, Science/Research, Education, Developers, Advanced End Users					Download Now!
The HDL Complexity Tool	8,917	96.83%	2008-04-11	2009-07-17	1,398
The HDL Complexity Tool parses large complex hardware projects' source code to produce useful complexity results. GOALS: 1)Practical, effective and simple 2) Integrates with existing design flows 3) Used on real projects 4) Based on existing research Topic: Hardware User Interface: Command-line Programming Language: VHDL/Verilog License: GNU Library or Lesser General Public License (LGPL) Intended Audience: Quality Engineers, Developers Development Status: 3 - Alpha					Download Now!
Welec W2000a	2,900	98.97%	2008-07-18	2009-07-15	3,450
Firmware development/ improvement for the digital storage oscilloscope "Welec 2000a- series". Topic: Visualization Programming Language: VHDL/Verilog, C++ License: GNU General Public License (GPL) Intended Audience: Advanced End Users Development Status: 5 - Production/Stable					Download Now!
FPGA-Based Oscilloscope	38,939	86.14%	2009-04-01	2009-07-06	586
Oscilloscope components, including 100MHz quad A/D, VHDL code for Xilinx FPGA, and driver for Octave or Matlab. Topic: Test and Measurement Programming Language: C, VHDL/Verilog Operating System: All POSIX (Linux/BSD/UNIX-like OSes) License: GNU General Public License (GPL) Intended Audience: Engineering, Advanced End Users Development Status: 3 - Alpha					Download Now!
crc-gen-verilog-vhdl	71,055	74.70%	2009-06-28	2009-06-28	390
CRC Generator is a command-line application that generates Verilog or VHDL code for CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The code is written in C for Win32, bus easily portable for other platforms Topic: Hardware User Interface: Command-line Programming Language: C, VHDL/Verilog Operating System: 32-bit MS Windows (NT/2000/XP) License: MIT License Intended Audience: Developers, Telecommunications Industry Development Status: 5 - Production/Stable					Download Now!
Verilog Tool Framework	3,310	98.82%	2007-02-12	2009-06-21	2,349
vrq is verilog parser that supports plugin tools to process verilog. Current plugins include tools to perform x-propagation and to auto build hiearchy. Topic: Electronic Design Automation (EDA) Programming Language: VHDL/Verilog Operating System: OS Portable (Source code to work with many OS platforms) License: GNU General Public License (GPL) Intended Audience: Developers Development Status: 5 - Production/Stable					Download Now!
GXSM	3,570	98.73%	2000-10-16	2009-06-21	13,612
A multi-channel image and vector-probe data acquisition and visualization system designed for SPM techniques (STM,AFM..), but also SPA-LEED. A plug-in interface allows any user add-on data-processing and special hardware and instrument support. Topic: Hardware Drivers, 3D Rendering, Visualization, Physics User Interface: Gnome, Plugins Translations: English, German, Esperanto Programming Language: C++, C, Python, VHDL/Verilog, Assembly Operating System: Linux, OS X, All POSIX (Linux/BSD/UNIX-like OSes), Fink (Mac OS X), Cygwin (MS Windows) License: GNU General Public License (GPL) Intended Audience: Science/Research, Education, Other Audience, Advanced End Users, Developers Development Status: 6 - Mature					Download Now!
vMAGIC	1,547	99.45%	2008-04-01	2009-06-17	713
vMAGIC is an Java-API which helps creating VHDL generators and analyzers. vMAGIC comprises of three parts: 1st a VHDL'93 compliant parser, 2nd a programming model to easily create and modify VHDL constructs and 3rd a VHDL Writer to generate code. Topic: Code Generators, Electronic Design Automation (EDA) Programming Language: VHDL/Verilog, Java Operating System: OS Independent (Written in an interpreted language) License: GNU Library or "Lesser" General Public License version 3.0 (LGPLv3) Intended Audience: Information Technology, Science/Research, Developers Development Status: 3 - Alpha					Download Now!
accellera-vip-interop-library	7,512	97.33%	2009-04-17	2009-06-10	227
This library supports interoperability between components written for different verification methodologies such as VMM and OVM. This is maintained by the Accellera Verification Intellectual Property Technical Subcommittee. Topic: Simulations, Electronic Design Automation (EDA) User Interface: Other toolkit Programming Language: VHDL/Verilog Operating System: OS Independent (Written in an interpreted language) License: Apache License V2.0 Intended Audience: Science/Research, Information Technology, Telecommunications Industry, Engineering, Advanced End Users, Developers Development Status: 1 - Planning					Download Now!
lfsr-counter-generator	69,465	75.27%	2009-05-23	2009-05-26	383
A command-line application that generates Verilog or VHDL code for an LFSR counter of any value up to 63 bit wide. The code is written in C for Win32 platform Topic: Other/Nonlisted Topic User Interface: Command-line Programming Language: C, VHDL/Verilog License: GNU General Public License (GPL), MIT License Intended Audience: Developers Development Status: 5 - Production/Stable					Download Now!