This is a Viterbi HDL Code Generator (VHCG). It can generate the Verilog HDL codes of some kind of Viterbi Decoder which is scalable and parameterized. In-place-state-metric-storage is used in these decoders. I purpose that it can reduce repeated works i
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viterbi-decoder example file released: k_9_rate_1-2_VHDL.rar
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viterbi-decoder example file released: Verilog_TD-SCDMA_rate_1-2_Viterbi_decoder.rar
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viterbi-decoder example file released: rag_91_121_TB120_RAMSIZE512x32.rar
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File released: /viterbi-decoder/example/rag_91_121_TB120_RAMSIZE512x32.rar
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File released: /viterbi-decoder/example/Verilog_TD-SCDMA_rate_1-2_Viterbi_decoder.rar
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Project Information Updated
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viterbi-gen release1.3 file released: morpheus1.3release.rar
%Version 1.3 Add Direct Traceback Option and Self test module Rejust the GUI Interface.
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File released: /viterbi-gen/release1.3/morpheus1.3release.rar
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File released: /viterbi-decoder/example/k_9_rate_1-2_VHDL.rar
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viterbi-gen version1.2 file released: morpheus1.2release.rar
%Version 1.1 Add synchronous ram surpport Redefine the interface and something else %Version 1.2 Adjust directory structure, remove "source" "data" directory, add "testvector" "sim" "bench" directory. Change negedge reset to posedge reset Add soft reset signal to traceback.v Some other changes, see the head in each file.
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