A verilog language compiler written using Java and JavaCC. It produces a netlist, an ascii text file, of all the cell connections. It can compile very large circuits comprised of many modules.
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File released: /Binaries/verilogx.jar
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File released: /README/README_FIRST.TXT
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File released: /README/Compiler Manual.pdf
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File released: /README/Verilog Parser Rights.pdf
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