Eclipse Verilog editor

Hi

I am using veditorv 0.7.0, eclipse 3.5.1

I have a testbench with all the verif tests in. (Reason for large file)

As soon as the vhdl file gets larger than +-500k, "Outline" stops working. (Hierarchy aswell)

I made a very simple test vhdl file. Same thing, >500k "Outline" stop working.

Is there a setting to inrease this file size limit?

Thanks

There's no line number limitation. The performance should only be limited by your computer's CPU/Memory. I have not tested the editor with large files but I 'll try in the near future. There is a slight chance we can improve the performance of the parser.

Hi, I found a limit in VhdlParser#parse:

        if(!ignorefile && filesize < 500000) {
            ASTdesign_file designFile=design_file();
            updateOutline(designFile);
            SemanticWarnings warn = new SemanticWarnings(m_File);
            warn.check(designFile);
        } else {
            ASTdesign_file designFile=new ASTdesign_file(JJTDESIGN_FILE);
            updateOutline(designFile);
        }