SVUnit

Systemverilog Unit Test Framework

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Description

SVUnit is a unit test framework for developers writing code in systemverilog. Verify systemverilog modules, classes and interfaces in isolation with SVUnit to eliminate bugs before they infest your design!

SVUnit Web Site

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Features

  • Generate all 3 layers of the SVUnit framework
  • Supports unit test templates for systemverilog modules, interfaces and classes
  • Supports unit testing of UVM components
  • Processes sub-directories recursively to aggregate unit tests into multiple testsuites
  • Compiles one or more testsuites into a single simulation executable
  • Supports Synopsys VCS, Mentor Questa and Cadence Incisive simulators
  • Reports PASS/FAIL result for each unit test, testsuite and aggregated test run
  • Supports unit testing of design, reference model and testbench code
  • Functioning examples of SVUnit applied to UVM components

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User Reviews

  • tudortimi
    1 of 5 2 of 5 3 of 5 4 of 5 5 of 5

    I've just gotten into unit testing and SVUnit is definitely what was missing for SystemVerilog. It may not be as feature rich as other xUnit platforms, but it's evolving at a very good pace.

    Posted 03/05/2014
  • vxl119
    1 of 5 2 of 5 3 of 5 4 of 5 5 of 5

    SVUnit is a must have for any SystemVerilog project.

    Posted 06/24/2013
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Additional Project Details

Registered

2011-11-21
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