by jrandrews
Source Navigator for Verilog is a verilog parser that allows Source Navigator to be used with the Verilog Hardware Description Language. http://sources.redhat.com/sourcenav
Anonymous created the doumentation required artifact
A new release is now available, version 2.1 It updates everything to the new Source Navigator 5.1.1 version and adds new verilog features including a new menu to lint, compile, simulate and debug your design.
netwenchang commented on the RE: Where is the Verilog Parser? forum thread
netwenchang created the Where is the Verilog Parser? forum thread
farzin created the Have problem using snavigator for verilog forum thread
jrandrews created the Thanks to all forum thread
Linux release of Source Navigator for Verilog ready for download. http://prdownloads.sourceforge.net/snverilog/snv-2.0.linux.tar.gz
A new version of Source Navigator for Verilog is now available. It uses a Perl parser instead of a Yacc based parser. It should take care of a lot of the parsing issues. Give it a try. http://snverilog.sourceforge.net/
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