Add a Review
1 Download (This Week)
Last Update:
Download smgen_0.1.tgz
Browse All Files
BSD Linux


SmGen is a finite state machine generator for Verilog. Not an FSM entry tool though. The input is behavioral-like Verilog. SmGen generates a synthesizabe FSM based design from it. Clock boundaries are explicitly provided by the designer.

SmGen Web Site

Update Notifications

Write a Review

User Reviews

Be the first to post a review of SmGen!

Additional Project Details

Intended Audience

Developers, Engineering, Science/Research

User Interface


Programming Language

Perl, VHDL/Verilog


Screenshots can attract more users to your project.
Features can attract more users to your project.

Icons must be PNG, GIF, or JPEG and less than 1 MiB in size. They will be displayed as 48x48 images.