SmGen

alpha

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BSD Linux

Description

SmGen is a finite state machine generator for Verilog. Not an FSM entry tool though. The input is behavioral-like Verilog. SmGen generates a synthesizabe FSM based design from it. Clock boundaries are explicitly provided by the designer.

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Additional Project Details

Intended Audience

Developers, Engineering, Science/Research

User Interface

Command-line

Programming Language

Perl, VHDL/Verilog

Registered

2010-06-11
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