HDL Analyzer and Netlist Architect (HANA): An open source analysis and synthesis tool for design written in Verilog 2001 HDL
sim-sim is perfect tool for synthesis, although I have noticed some problems with output formatting, netlist optimalization and absence of documentation.
Sim-sim works excellent.
This project is AWESOME! Please present it more prominently so others can find it easier. At first I didn't try it because there was so little information here..