SystemC Logic Analyzer

prealpha
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Description

HW(VHDL) and SW of logic analyzer and On-Chip-Verification(OCV) for Value Change Dump(VCD) file format that exported to seemd SystemC ,ModelSIM, and many other EDA tools. Very easy and Simple.

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Additional Project Details

Languages

English

Intended Audience

Advanced End Users, Developers

User Interface

GTK+

Programming Language

C, VHDL/Verilog

Registered

2007-07-17
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