scicosHDL

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simulation circuit diagram synthesized 74138' HDL generated by Scicos HDL by Synplify D trigget synthesizedby by Synplify Peripheral circuit of single chip synthesize by Synplify 4-bit-couter

Description

Scicos-HDL is a tool to design digital circuit system; it integrates the hardware circuit, algorithm and Scilab/Scicos environment as a plat for digital circuit design, simulation and Hardware Description Language generation. ZhangDong & KangCai

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Email, MSN Messenger, Window Managers

License

GNU Library or Lesser General Public License version 2.0 (LGPLv2)

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Additional Project Details

Languages

Chinese (Simplified), English

Intended Audience

Developers, Education, Healthcare Industry, Science/Research, Telecommunications Industry

User Interface

Tk

Programming Language

C, IDL, Tcl, VHDL/Verilog

Registered

2006-07-24

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