Scicos-HDL is a tool to design digital circuit system; it integrates the hardware circuit, algorithm and Scilab/Scicos environment as a plat for digital circuit design, simulation and Hardware Description Language generation. ZhangDong & KangCai
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scicoshdl_v06 scicoshdl_v06.zip file released: scicoshdl_v06.zip
--scicos-hdl 0.6 (2004-2009) --Copyright NXU AGL, LIAMA, ZhangDong&KangCai --vhdl / verilog compiler 2006 3 --SystemC compiler 2008 8 --verilog compiler 2006 6.2 --simulation engineen 2009.5
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File released: /scicoshdl_v06/scicoshdl_v06.zip/scicoshdl_v06.zip
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scicoshdl032 scicoshdl032.zip file released: ScicosHDL032_NEW.zip
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File released: /scicoshdl032/scicoshdl032.zip/ScicosHDL032_NEW.zip
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HART Toolbox for Scilab/Scicos
The HART (Hardware Access in Real-Time) Toolbox can be used to generate Scicos-blocks for hardware that have a C/C++ interface. The blocks can be used under Linux for soft and hard real time tasks (RTAI). Blocks are provided for DAQ (COMEDI, Labjack).
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