by sforbes
PVSim is a Verilog Simulator for Mac OS X that uses AlphaX editor's Verilog mode and features a fast compile-simulate-display cycle.
Version 5.6.0 -- Improvements since 5.5.0:
Language
========
r1655 Added auto-generation of "module_instance" module names in leu of full
parameter support.
Improved $readmemmif() to handle hex addresses and 32-bit data.
r2214 ...
Version 5.6.0 -- Improvements since 5.5.0:
Language
========
r1655 Added auto-generation of "module_instance" module names in leu of full
parameter support.
Improved $readmemmif() to handle hex addresses and 32-bit data.
r2214 ...
Version 5.5.0 -- Improvements since 5.4.0b1:
Language
========
Standardized $display() statements.
Added $fopen() and $fdisplay() system functions.
Fixed $display(), $fdisplay(): now auto-newline, convert args to integers,
accept %t and %h ...
Version 5.5.0 -- Improvements since 5.4.0b1:
Language
========
Standardized $display() statements.
Added $fopen() and $fdisplay() system functions.
Fixed $display(), $fdisplay(): now auto-newline, convert args to integers,
accept %t and %h ...
Anonymous committed patchset 1 of module CVSROOT to the PVSim Verilog Simulator CVS repository, changing 11 files
registered the PVSim Verilog Simulator project
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