An experimental ISS for freescale's e500v2 core. It is meant to simulate only cpu and memory subsystem and is purely intended for academic/learning purposes only.
- full support of booke mmu emulation ( l2 tlbs only ).
- support for a target based memory model ( targetting DDR, CCSR and IFC for time being )
- support for a well tested logging framework.
- support for an interactive python shell to control the simulation environment.
- support for an elf loader to directly load elf binaries in memory.
- support for powerpc exception mechanism.
- all core instructions except SPE are implemented.
- support for instruction tracing and coverage logging.
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