In comparison to other emulators this one doesn't gives you the complete instruction cycle count but the consumed cycles more times per instruction.
By each memory access during the instruction you have knowledge about how many cycles have passed so far. So you could sync up your other concurrent tasks before accessing system bus
- includes unit tests for all opcodes (*)
- cycle usage callback for each single step
- starts prefetching at correct cycle times (**)
- starts irq sampling at correct cycle times (**)
- accurate exception processing (***)
(*) unit test samples were generated with amiga
(**) information is taken from patent and manual, not proven with logic analyzer
(***) needs more testing
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