Orchestra, a SoC Generator

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Description

The main target of this project is to create a Open Source System on Chip generator for FPGA. This generator will use following technologies: Python, Wishbone SoC bus specifications and VHDL.

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Additional Project Details

Intended Audience

Developers, Other Audience

User Interface

Console/Terminal

Programming Language

Python, VHDL/Verilog

Registered

2008-03-13
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