Netlist Modifier for Implicit-style VHDL

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Description

This Program will modify the netlist(edf file) generated by a vhdl synthesis tool of a Implicit style VHDL Model, so that the propagation delay caused by signals are removed, so that the post synthesis do match the ideal and pre-synthesis analysis.

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Additional Project Details

Languages

English

Intended Audience

Education

User Interface

Win32 (MS Windows)

Programming Language

C, C++

Registered

2006-10-25
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