Modular, Configurable Simulator for Computer Architects
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We're happy to announce an official beta release of M5 2.0, including all the new features described at our ISCA 2006 tutorial: - A new execute-in-execute detailed out-of-order CPU model - A new memory system - More extensive python integration - Preliminary syscall emulation support for MIPS and SPARC We are still working out a few kinks, particularly in the area of MP coherence support in the new memory system. We hope to have these issues resolved soon, and will put out an official 2.0 release when they are complete. In the meantime, we wanted to make the code base available for those that don't need MP support, or who otherwise would like a preview of the new 2.0 features. For more information (including updated documentation and download links) go to http://www.m5sim.org. Also, please take a look at the new July/August issue of IEEE Micro, which includes an article on M5.
M5 is slowly moving away from SourceForge to our own server at http://www.m5sim.org. As one step in that transition, we are deprecating the SourceForge-hosted mailing lists in favor of two new mailing lists: m5-users@m5sim.org m5-announce@m5sim.org If you were previously subscribed to the SourceForge m5sim-users or m5sim-announce lists, you should have been automatically subscribed to the appropriate new list. For more information, see http://www.m5sim.org/wiki/index.php/Mailing_Lists.
M5 release 1.1 is now available. This is an update release coinciding with the mini-tutorial being given at the IOSCA workshop (http://www.ideal.ece.ufl.edu/iosca). New features include: - Preliminary FreeBSD support - Integration of regression tests into scons build framework - Several bug fixes and better compatibility for Cygwin hosts - Major cleanup of Alpha system code (console, PAL, etc.) to make it easier for others to build/modify - Fixes to enable compilation under g++ 4.0 - Numerous minor bug fixes
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