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Logic Circuit Simulation in C++ Icon

Logic Circuit Simulation in C++

beta

by sivachandra


libLCS is a hardware description library in C++ aiming to be as powerfull and easy as the Verilog HDL. It currently supports logic gates, flipflops, clock, and facilitates delays, continuous assignments and variable value dumping into VCD files.

Browse Files for Logic Circuit Simulation in C++

File/Folder Name  Platform Size Date ↓ Downloads Notes/Subscribe
Subdirectory (view all files)
liblcs 218.8 KB 2006-10-14 46 Subscribe Folder view
libLCS-0.0.21 218.8 KB 2006-10-14 46 Subscribe Folder view
libLCS-0.0.21.zip 218.8 KB 2006-10-14 46