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Logic Circuit Simulation in C++

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Programming Languages: C++

License: GNU Library or Lesser General Public License (LGPL), GNU General Public License (GPL)

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browse code, statistics, last commit on 2006-09-18 cvs -d:pserver:anonymous@liblcs.cvs.sourceforge.net:/cvsroot/liblcs login

cvs -z3 -d:pserver:anonymous@liblcs.cvs.sourceforge.net:/cvsroot/liblcs co -P modulename

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  • Comment: Shift Register

    This feature now available with libLCS-0.0.59 and hence the request is closed. Submit bug if you find any through the bug tracker.

    2007-10-25 04:06:52 UTC by sivachandra

  • Shift Register

    A shift register should be provided as an off-the-shelf utitlity classes. The number of bits in the register should be a template parameter for the ShiftRegister template module class. The shift operation should occur at the occurance of a line event on the clock input.

    2007-09-03 13:51:08 UTC by sivachandra

  • libLCS-0.0.56 Released

    libLCS-0.0.56 has been released. You can download it using the download links provided on the libLCS project page on sourceforge.net. With this release, one can implement modules as a hybrid of other block level and behavioral models. The complete changelog for libLCS-0.0.56 can be obtained under the news section of the project website. Also, check the libLCS blog for updates on the happenings...

    2007-07-23 03:59:05 UTC by sivachandra

  • Comment: Bus bit-selects as module ports

    This feature is available with libLCS-0.0.55 and later.

    2007-04-22 09:51:22 UTC by sivachandra

  • libLCS-0.0.55 Released

    libLCS-0.0.55 has been released. You can download it using the download links provided on the libLCS project page on sourceforge.net. With this release, one can use bitselects as module ports. A new example, illustrating this new feature, has been added. The complete changelog for libLCS-0.0.55 can be obtained under the news section of the project website. Also, check the libLCS blog for updates...

    2007-04-21 10:49:54 UTC by sivachandra

  • Bus bit-selects as module ports

    Bus bit selects should be allowed as module ports. Following is a sample usage: Bus b; // Bit-selects on the bus b are used as module ports. And andGate(b[0], (b[1], b[2]));.

    2007-04-18 08:10:37 UTC by sivachandra

  • Comment: Implementing hybrids of functional and block level modules

    I have figured out a way to implement modules which are a hybrid of other modules and functional/behaviourial constructs. This does not require any new feature to be added to libLCS. One can start implementing hybrid modules right away if he/she understands the event propogation scheme of libLCS. I plan to provide thorough guidelines for this in the userguide. Kindly check the userguide for more...

    2007-04-12 07:16:59 UTC by sivachandra

  • Comment: suggestions

    libLCS-0.0.53 has been released. This release contains a FanOut module which provides the requested functionality.

    2007-03-08 05:07:13 UTC by sivachandra

  • Comment: Compilation error with JK flipflop module

    This problem has been fixed in libLCS-0.0.53 and hence the patch is now closed.

    2007-03-08 05:05:44 UTC by sivachandra

  • Comment: suggestions

    The FanOut module will be provided with libLCS-0.0.53. The gate generator module you have mentioned is very similar to a flipflop. A special class will not provided further.

    2007-03-01 06:59:09 UTC by sivachandra

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