Deal with unimplemented functions by running handler.
Re-simplify Register interface .. just read/write.
Remove IBUS/OVF internals in favour of conf.ovf etc.
64-bit corrections and do ALU via decomposition to 32, 16 and 8 bit
Trial port of 64-bit version from 1.3b.
Add CPU6 and CPU7. Documentation updated from Wiki throughout.
Correct branch delay-slot handling, in which the instr after a jump or
branch is always executed. Switched on with CPU_BRANCH_DELAY_SLOT=1.
Irqs immediately following a delay slot needed to know the orig branch or
jump destination in order to set EPC correctly, so implemented that.
Complete cycle of known bug-fixes.
Fix ORI, XORI, ANDI bug (16 bit immediate val should be zero-extended always,
Remove obscure lock cycle between Screen (print), Keyboard (read) and CPU.
Even some corrections in ALU, which now gets an overflow flag.
Retract half-baked MIPS delay-slot implementation to make sure timing
stays stable - and code too. So 1.7a just contains the bug fixes from
1.7 over 1.6.
Add treatment of LT to ALU.
Fix JALR bug in CPU2-5.
Increase IOBus speed to 66MHz to help optimization of hello_world.
Increase Console buffer to 4096 to allow CPU1-4 to output more than
128 chars on the dhrystone benchmark.
FIx SLT and SLTU bug in ALU.
Clear up some kind of DIV or MFLO -related bug that disappeared without
me being able to be sure what it was. Will probably reappear. Notice
that gcc seems to generate assembler for c=a/b that depends on the
instr after a branch being executed. It produces
bnez b, FOO
It's a silly save of one instr. It could be
bnez b, FOO
My compile options are
-O0 -static -DMIPS -mips1 -mabi=32 -msoft-float -mno-memcpy
gcc version 4.3.5 (Debian 4.3.5-4).
I've now arranged for this delay slot to be executed in CPU2-5. In CPU5
I've forbidden IRQ to interrupt a jump or branch, to avoid flushing the
delay slot following. In CPU2-5 jump or branch don't flush the
following instr in the pipeline. Don't know what to do in CPU1.
I've also made ELF more sophisticated I hope. It loads sections
Remove a bug in Register behaviour that was making life too easy.
Registers should have shown a written value for read only on the next
clock, but that did not always happen (simply: buggy code). That
permitted instructions to be in the pipeline together that should never
have been in there at the same time, as one wrote what the other wanted
However, a bug in the pipeline Read stage (off-by-one bug) allowed it,
and no misbehaviour accrued because of the Register bug.
From the outside, speeds were showing up as too high for the level of
hardware optimization, since instructions could be - and were - crowded
closer in the pipeline than they should have been.
Remove more printfs so that older Javas can compile and run the code.
Refine locking in CPU5 so that IRQ and IACK changes are locked and
signalled through cpu, while the Clock (class) is reserved for
signalling time-based events. That fixes a rare deadlock due
(presumably) to somehow peripherals running code synchronized on the
clock and vice-versa (without flagging every entry into a synchronized
block I can't locate the problem, but it looks that way).
Provide 64-bit utility routines for possible cache use.
Mend bug in CPU5 that tested for JALR wrongly in Irq stage and resulted
in sporadic loop on SMP platforms doing return from RFE to addr 0.
Remove printf references in favour of print, so that can run under
kaffe (1.1.8, java 1.4) and jamvm (1.5.1, java 1.5) as well as under
the openjdk JVM (1.6.0, java 1.6).
Registers flip on a clock edge only. Writes aren't readable until after
next clock tick.