Interconnection Network Generator

alpha
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Description

WISHBONE bus generator for multiprocessor systems. Started at the University of Ottawa, this project provides users with access to an API and a GUI. The output language is VHDL.

Interconnection Network Generator Web Site

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Additional Project Details

Intended Audience

Information Technology, Science/Research, Telecommunications Industry

User Interface

Eclipse, Java Swing

Programming Language

Java

Registered

2008-02-12
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