AIC-P1-ProcesadorSegmentado

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Description

Práctica para la asignatura Arquitectura e Ingeniería de Computadores de 4º curso de Ingeniería Informática (Universidad de Extremadura).
Simulación en VHDL de un procesador segmentado.

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Additional Project Details

Languages

Spanish

Intended Audience

Engineering

Programming Language

VHDL/Verilog

Registered

2009-10-04
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