High Performance IC Timing

planning
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BSD Linux

Description

A static timing analysis program written in C++. Cadence LEF/DEF definitions of circuit geometry and SDF definitions of circuit timing data of a synchronous circuit are compiled in order to generate timing constraints for non-zero skew circuit operation.

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Additional Project Details

Languages

English

Intended Audience

Science/Research

Programming Language

C++

Registered

2004-01-05
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