FSMDesigner4 is a C++ based implementation for a Finite State Machine (FSM) design tool with integrated Hardware Description Language (HDL) generation. FSMDesigner4 uses the Simple-Moore FSM model guaranteeing efficient fast complex control circuits.
http://ra.ziti.uni-heidelberg.de/index.php?page=projects&id=fsmdes4
Wouldn't compile Wouldn't install No help available
Implemented SVG export, printing should work, improved state mnenonic map (include color), implement mnenonic maps for complete projects, and several small bugfixes. Additionally, version 1.2 adds System Verilog Assertions as an option for the HDL output thus supporting efficient verification including coverage analysis.
Version 1.2 was released today. This version improves several parts and introduces some new features. The main new features are .svg export and System Verilog Assertions (SVA) support for verification. Using this feature it is possible for example to get a coverage analysis of your FSM simulation. Improvements include fixes in printing and mnenonic map generation. We still need testers both for the application and the build process.
* more intuitive property editing * fixed many build-related problems * building tested on OpenSuSE 10.2 & 10.3 * need more testers...
Version 1.1 was released today. This version incorporates many build related improvements as well as more intuitive property editing. The configure script now actually tests for required librariess and programs; the property widget immediately updates the FSM view. Building has been tested on OpenSuSE 10.2 & 10.3. Testers needed!
The FSMDesigner subversion respository has moved from our own servers to sourceforge.net. Also, the wiki is online. Currenlty installation and open tasks are documented. We hope to add more soon.
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