MOVED TO https://github.com/tommythorn/yari
THIS IS DEAD - project moved to https://github.com/tommythorn/yari
YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includes a complete SoC, simulator, GDB stub, scripts, and various examples.
- Classic five stage pipeline
- 4-way associative instruction and data cache with store buffer
- Assorted system components, including memory controllers, video, serial, etc.
Thanks for updates ;)