FPGA Build Tool

beta
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Description

Automatic build management for VHDL and Verilog projects. The automatic dependency resolver finds the exact subset of sources, and the correct order they must appear in required to build a project. A Makefile automates the actual build itself.

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Additional Project Details

Intended Audience

Developers, Science/Research

User Interface

Command-line

Programming Language

VHDL/Verilog

Registered

2008-12-03
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