EziDebug

simulation tool for verification and debugging of digital circuits

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Description

EziDebug is an easy-to-use versatile logic simulation tool for verification and debugging of digital circuits. It supports inserting scan chains in projects. Furthermore,more functions and characteristics will be opened. This manual is intended for users with no previous experience with EziDebug . It introduces you with the basic flow how to set up EziDebug. The example used in this tutorial is a small design written in Verilog and only the most basic commands will be covered in this manual. This manual was made by using Version 1.0 of EziDebug on Windows.

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User Reviews

  • zhangdb
    1 of 5 2 of 5 3 of 5 4 of 5 5 of 5

    it is a perfect tool for my work!

    Posted 08/26/2013
  • leionway73
    1 of 5 2 of 5 3 of 5 4 of 5 5 of 5

    this is a very useful tool for fpga debug

    Posted 07/31/2013
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Additional Project Details

Languages

Chinese (Simplified)

Intended Audience

Engineering, Testers

User Interface

Qt, Win32 (MS Windows)

Programming Language

C, C++

Registered

2012-11-28
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