This project's goal is to provide a simple but extendable SOC (System On Chip) that can be loaded into an FPGA in order to quickly test custom coprocessors and evaluate their robustness against SCA (Side Channel Attacks) or others physical attacks.
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evesoc evesoc-r0.1 file released: evesoc-r0.1.tgz
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EveSoc R 0.1
The Release 0.1 of EveSoc has been committed.
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File released: /evesoc/evesoc-r0.1/evesoc-r0.1.tgz
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