This is a formal equivalence checking tool developed @ IIT Guwahati which can be used to verify functional equivalence between circuits (combinational and sequential) of the formats BLIF, verilog and EDIF.
Release Date:
2009-07-02
Topic:
License:
Programming Language:
Registered:
2008-11-18
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equiitg equiitg_1.2 beta file released: equiitg_1.2beta.tar.gz
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equiitg equiitg_1.2 beta file released: verified_benchmarks_1.2.tar.gz
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File released: /equiitg/equiitg_1.2 beta/verified_benchmarks_1.2.tar.gz
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File released: /equiitg/equiitg_1.2 beta/equiitg_1.2beta.tar.gz
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equiitg equiitg - 1.1 beta file released: equiitg_1.1beta.tar.gz
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equiitg equiitg - 1.1 beta file released: verified_benchmarks.tar.gz
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File released: /equiitg/equiitg - 1.1 beta/verified_benchmarks.tar.gz
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File released: /equiitg/equiitg - 1.1 beta/equiitg_1.1beta.tar.gz
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equiitg equiitg-1.0 file released: equiitg-1.0.tar.gz
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equiitg equiitg-1.0 file released: verified_examples.tar.gz
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