EduCPU

prealpha

Simple CPU for education

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Description

This is a simple CPU design, written in Verilog, intended for educational purposes. The objective is to provide a simulatable processor where the source code exposes concepts in CPU microarchitecture.

EduCPU Web Site

Categories

Hardware, Education

License

BSD License, MIT License

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Additional Project Details

Intended Audience

Science/Research, Education

Programming Language

VHDL/Verilog

Registered

2014-07-23
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