This project develops a DSP processor that is optimized for FIR/IIR/DCT operations. The coding is done in VHDL, and is intended to be synthesized by Altera Quartus II.
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removed tb_xxx and 8x8_xx files, added sonata project files and sample test waveform file.
The DSP core works with the FIR testbench as of now. Some more testing will be done in the next few days, and IIR and DCT will most likely work with the current version, too.
some of the tristate buffer logic changed, MAC to behavioral architecture, changed instruction format for the two memories (separate commands now), etc...
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