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cMIPS - an FPGA ready VHDL model for 5-stage pipeline, MIPS32r2 core

As of 2015-03-14, this project may now be found at https://gitlab.c3sl.ufpr.br/roberto/cmips.

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cMIPS says the best way to get help with its software is by visiting http://sourceforge.net/p/cmips/wiki.

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Project Homepage

This project has a homepage which can be found at http://www.inf.ufpr.br/roberto/cMIPS.html.