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This project aim to develop a suite of tool to ease the development of ASIC/FPGA solution. The final program should be an IDE enabling the creation and specification of a project from it's start to finish.

ChipIDE Web Site


  • netlist extractor from edn for one chip
  • netlist to ucf creator

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Additional Project Details

Intended Audience


User Interface

Command-line, Project is a templating system, Qt

Programming Language

C++, VHDL/Verilog


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