File Release Notes and Changelog
Notes:
Adam Brooks (2):
iop13xx: clean up xscale oprofile support and add xsc3 support
iop13xx: add oprofile support for the internal performance monitor
Dan Williams (34):
iop3xx: fix the ioremap implementation to not remap static ranges
do_undefinstr: read svc undefined instructions with svc privileges
iop: cp6 access handler (undef_hook)
entry: introduce get_irqnr_preamble and arch_ret_to_user
iop: remove cp6_enable/disable routines
iop: unify time implementation across iop32x, iop33x, and iop13xx
iop13xx: add resource definitions for the tpmi units
iop3xx: define IOP3XX_REG_ADDR[32|16|8] and clean up DMA/AAU defs
iop3xx: Give Linux control over PCI (ATU) initialization
ARM: allow DMA_NONE in consistent_sync
dmaengine: add base support for the async_tx api
ARM: Add drivers/dma to arch/arm/Kconfig
dmaengine: add the async_tx api
md: add raid5_run_ops and support routines
md: use raid5_run_ops for stripe cache operations
md: move write operations to raid5_run_ops
md: move raid5 compute block operations to raid5_run_ops
md: move raid5 parity checks to raid5_run_ops
md: satisfy raid5 read requests via raid5_run_ops
md: use async_tx and raid5_run_ops for raid5 expansion operations
md: move raid5 io requests to raid5_run_ops
md: remove raid5 compute_block and compute_parity5
dmaengine: driver for the iop32x, iop33x, and iop13xx raid engines
iop13xx: Surface the iop13xx adma units to the iop-adma driver
iop3xx: Surface the iop3xx DMA and AAU units to the iop-adma driver
i2c: m41st85w chip driver (real time clock)
iop13xx: enable 36-bit pci resources to be mapped into userspace
iop13xx: workarond errata that causes uart interrupts to be missed
ARM: revert patch 2723/2 for 64-bit divide support
iop: polling mode pbi compact flash driver
async_tx: use an offload engine for copy_page, copy_user_page, and clear_page
async_tx: divert large in-kernel memcpy calls to a dma engine
sata_vsc: handle unexpected interrupts when executing a polled IDENTIFY
v2.6.20-iop1
Daniel Wolstenholme (1):
iop13xx: msi support
David Brownell (1):
rm pointless dmaengine exports
Greg Tucker (3):
iop13xx: add base support for the imu
iop13xx: imu scsi driver
iop13xx: support receiving a reset message from the other core
Changes:
commit c69b7d5e0a5bc154c0dc88d4bc14a86000dea58a
Author: Dan Williams <dan.j.williams@intel.com>
Date: Tue Jan 2 13:52:32 2007 -0700
v2.6.20-iop1
[ not for upstream ]
commit 2ef7d994cd38f37c0f6a96146a39efe8cb444e7f
Author: Dan Williams <dan.j.williams@intel.com>
Date: Fri Feb 9 17:47:47 2007 -0700
sata_vsc: handle unexpected interrupts when executing a polled IDENTIFY
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
commit 4e8ac88efe0ccf42186c5e7252e27de3d47ecf44
Author: Dan Williams <dan.j.williams@intel.com>
Date: Fri Feb 9 17:47:47 2007 -0700
async_tx: divert large in-kernel memcpy calls to a dma engine
[ experimental ]
commit 7047bd9ea0cbac5136fdd792125d94706eb8d2b0
Author: Dan Williams <dan.j.williams@intel.com>
Date: Fri Feb 9 17:47:46 2007 -0700
async_tx: use an offload engine for copy_page, copy_user_page, and clear_page
[ experimental ]
commit 978fc02e33a9dff7eb95fc88ae09f6d0f6acafbd
Author: Dan Williams <dan.j.williams@intel.com>
Date: Tue Jan 2 13:52:32 2007 -0700
iop: polling mode pbi compact flash driver
[ experimental ]
commit 9e5a3d4e2c9c8a04c1b9b3a07e73c2d0dda5c23c
Author: Dan Williams <dan.j.williams@intel.com>
Date: Tue Jan 2 13:52:32 2007 -0700
ARM: revert patch 2723/2 for 64-bit divide support
This patch supports a customer request for __udivdi3, __umoddi3, and
__udivmoddi4 support, but Russell's position, which I support, is that code
should be re-written to not use these symbols.
[ not for upstream ]
commit a1e50d491a328e9df0dbecca9d432b5a48e8d1e7
Author: Dan Williams <dan.j.williams@intel.com>
Date: Wed Sep 20 17:35:26 2006 -0700
iop13xx: workarond errata that causes uart interrupts to be missed
Reading the uart iir register is meant to clear the interrupt and
simultaneously report that an interrupt was pending. Sometimes the
interrupt is cleared but the pending status is not reported. Use the the
system interrupt pending register as a fall back.
[ not for upstream ]
commit 93ae3fec029410cb3bde84c5f0703c7b58be384d
Author: Greg Tucker <greg.b.tucker@intel.com>
Date: Tue Jan 2 13:52:32 2007 -0700
iop13xx: support receiving a reset message from the other core
[ not for upstream ]
commit b3791eca611232f9d396ff4d10c76fa98fa40cd5
Author: Adam Brooks <adam.j.brooks@intel.com>
Date: Tue Jan 2 13:52:31 2007 -0700
iop13xx: add oprofile support for the internal performance monitor
[ not for upstream ]
commit a9e2ecfc2b9ce6426a0659681a6d48428384c1c5
Author: Dan Williams <dan.j.williams@intel.com>
Date: Tue Jan 2 11:10:41 2007 -0700
iop13xx: enable 36-bit pci resources to be mapped into userspace
iop13xx pci space is only accessible via 36-bit addressing, so it is not
able to use the standard remap_pfn_range routine in pci_mmap_page_range.
This patch adds the capability for different ARM architectures to define
their own pci_mmap_page_range routine and enables the capability for
iop13xx.
The remap_supersection_range implementation was copied from Lennert
Buytenhek's implementation in:
http://svn.wantstofly.org/kernel/mmap-supersections.diff
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
commit 06e5908fc49d343ca4970ba7ae51a3a58940e74e
Author: Dan Williams <dan.j.williams@intel.com>
Date: Thu Oct 19 22:18:05 2006 -0700
i2c: m41st85w chip driver (real time clock)
to do: enable the m41t00 for ARM
[ not for upstream ]
commit a528653b59cdc385797671178895d57acbec4b2c
Author: Dan Williams <dan.j.williams@intel.com>
Date: Tue Jan 2 13:52:31 2007 -0700
iop3xx: Surface the iop3xx DMA and AAU units to the iop-adma driver
Adds the platform device definitions and the architecture specific support
routines (i.e. register initialization and descriptor formats) for the
iop-adma driver.
Changelog:
* add support for > 1k zero sum buffer sizes
* added dma/aau platform devices to iq80321 and iq80332 setup
* fixed the calculation in iop_desc_is_aligned
* support xor buffer sizes larger than 16MB
* fix places where software descriptors are assumed to be contiguous, only
hardware descriptors are contiguous
for up to a PAGE_SIZE buffer size
* convert to async_tx
* add interrupt support
* add platform devices for 80219 boards
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
commit 44442c10f04c7966fd57282e3b1256ddc366711c
Author: Dan Williams <dan.j.williams@intel.com>
Date: Tue Jan 2 13:52:31 2007 -0700
iop13xx: Surface the iop13xx adma units to the iop-adma driver
Adds the platform device definitions and the architecture specific
support routines (i.e. register initialization and descriptor formats) for the
iop-adma driver.
Changelog:
* added 'descriptor pool size' to the platform data
* add base support for buffer sizes larger than 16MB (hw max)
* build error fix from Kirill A. Shutemov
* rebase for async_tx changes
* add interrupt support
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
commit e85fddf6cff40a20e26765ec80b732b5ef9a8a95
Author: Dan Williams <dan.j.williams@intel.com>
Date: Tue Jan 2 13:52:26 2007 -0700
dmaengine: driver for the iop32x, iop33x, and iop13xx raid engines
This is a driver for the iop DMA/AAU/ADMA units which are capable of pq_xor,
pq_update, pq_zero_sum, xor, dual_xor, xor_zero_sum, fill, copy+crc, and copy
operations.
Changelog:
* fixed a slot allocation bug in do_iop13xx_adma_xor that caused too few
slots to be requested eventually leading to data corruption
* enabled the slot allocation routine to attempt to free slots before
returning -ENOMEM
* switched the cleanup routine to solely use the software chain and the
status register to determine if a descriptor is complete. This is
necessary to support other IOP engines that do not have status writeback
capability
* make the driver iop generic
* modified the allocation routines to understand allocating a group of
slots for a single operation
* added a null xor initialization operation for the xor only channel on
iop3xx
* support xor operations on buffers larger than the hardware maximum
* split the do_* routines into separate prep, src/dest set, submit stages
* added async_tx support (dependent operations initiation at cleanup time)
* simplified group handling
* added interrupt support (callbacks via tasklets)
* brought the pending depth inline with ioat (i.e. 4 descriptors)
* drop dma mapping methods, suggested by Chris Leech
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
commit 23acfc83232a32f0c14eb4bd9e11e88dd9f2ebcb
Author: Dan Williams <dan.j.williams@intel.com>
Date: Tue Jan 2 13:52:31 2007 -0700
md: remove raid5 compute_block and compute_parity5
replaced by raid5_run_ops
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
commit dfa4d67570aac6cb43a36309643d8bbdf7630984
Author: Dan Williams <dan.j.williams@intel.com>
Date: Tue Jan 2 13:52:31 2007 -0700
md: move raid5 io requests to raid5_run_ops
handle_stripe now only updates the state of stripes. All execution of
operations is moved to raid5_run_ops.
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
commit 1411f1ad18919595d8f919ae3d5d25899e63af8c
Author: Dan Williams <dan.j.williams@intel.com>
Date: Tue Jan 2 13:52:31 2007 -0700
md: use async_tx and raid5_run_ops for raid5 expansion operations
The parity calculation for an expansion operation is the same as the
calculation performed at the end of a write with the caveat that all blocks
in the stripe are scheduled to be written. An expansion operation is
identified as a stripe with the POSTXOR flag set and the BIODRAIN flag not
set.
The bulk copy operation to the new stripe is handled inline by async_tx.
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
commit 8b5dc8da1873a3fc29b5fea7509c5efd100b2b04
Author: Dan Williams <dan.j.williams@intel.com>
Date: Tue Jan 2 13:52:31 2007 -0700
md: satisfy raid5 read requests via raid5_run_ops
Use raid5_run_ops to carry out the memory copies for a raid5 read request.
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
commit f15409622bb1b2fa0f2a100e864b4e140754b015
Author: Dan Williams <dan.j.williams@intel.com>
Date: Tue Jan 2 13:52:31 2007 -0700
md: move raid5 parity checks to raid5_run_ops
handle_stripe sets STRIPE_OP_CHECK to request a check operation in
raid5_run_ops. If raid5_run_ops is able to perform the check with a
dma engine the parity will be preserved in memory removing the need to
re-read it from disk, as is necessary in the synchronous case.
'Repair' operations re-use the same logic as compute block, with the caveat
that the results of the compute block are immediately written back to the
parity disk. To differentiate these operations the STRIPE_OP_MOD_REPAIR_PD
flag is added.
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
commit cb71d0d1226df2d1b318c183080afd32772da54b
Author: Dan Williams <dan.j.williams@intel.com>
Date: Tue Jan 2 13:52:30 2007 -0700
md: move raid5 compute block operations to raid5_run_ops
handle_stripe sets STRIPE_OP_COMPUTE_BLK to request servicing from
raid5_run_ops. It also sets a flag for the block being computed to let
other parts of handle_stripe submit dependent operations. raid5_run_ops
guarantees that the compute operation completes before any dependent
operation starts.
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
commit ac524202053404d7a9bd49ca5b64c0751cb8978a
Author: Dan Williams <dan.j.williams@intel.com>
Date: Tue Jan 2 13:52:30 2007 -0700
md: move write operations to raid5_run_ops
handle_stripe sets STRIPE_OP_PREXOR, STRIPE_OP_BIODRAIN, STRIPE_OP_POSTXOR
to request a write to the stripe cache. raid5_run_ops is triggerred to run
and executes the request outside the stripe lock.
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
commit 6201af1669cd04750faeddf518a0c363bb1537b3
Author: Dan Williams <dan.j.williams@intel.com>
Date: Tue Jan 2 13:52:30 2007 -0700
md: use raid5_run_ops for stripe cache operations
Each stripe has three flag variables to reflect the state of operations
(pending, ack, and complete).
-pending: set to request servicing in raid5_run_ops
-ack: set to reflect that raid5_runs_ops has seen this request
-complete: set when the operation is complete and it is ok for handle_stripe5
to clear 'pending' and 'ack'.
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
commit 37655cf41e16b917efc19ab9d42117889460abe1
Author: Dan Williams <dan.j.williams@intel.com>
Date: Tue Jan 2 13:52:30 2007 -0700
md: add raid5_run_ops and support routines
Prepare the raid5 implementation to use async_tx for running stripe
operations:
* biofill (copy data into request buffers to satisfy a read request)
* compute block (generate a missing block in the cache from the other
blocks)
* prexor (subtract existing data as part of the read-modify-write process)
* biodrain (copy data out of request buffers to satisfy a write request)
* postxor (recalculate parity for new data that has entered the cache)
* check (verify that the parity is correct)
* io (submit i/o to the member disks)
Changelog:
* removed ops_complete_biodrain in favor of ops_complete_postxor and
ops_complete_write.
* removed the workqueue
* call bi_end_io for reads in ops_complete_biofill
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
commit befa0867c816c0e904e9411b3e5d131ff5414eba
Author: Dan Williams <dan.j.williams@intel.com>
Date: Tue Jan 2 11:10:44 2007 -0700
dmaengine: add the async_tx api
async_tx is an api to describe a series of bulk memory
transfers/transforms. When possible these transactions are carried out by
asynchrounous dma engines. The api handles inter-transaction dependencies
and hides dma channel management from the client. When a dma engine is not
present the transaction is carried out via synchronous software routines.
Xor operations are handled by async_tx, to this end xor.c is moved into
drivers/dma and is changed to take an explicit destination address and
a series of sources to match the hardware engine implementation.
When CONFIG_DMA_ENGINE is not set the asynchrounous path is compiled away.
Changelog:
* fixed a leftover debug print
* don't allow callbacks in async_interrupt_cond
* fixed xor_block changes
* fixed usage of ASYNC_TX_XOR_DROP_DEST
* drop dma mapping methods, suggested by Chris Leech
* printk warning fixups from Andrew Morton
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
commit a21bfe50923967c8d29d0c4f184e740e8b17709c
Author: Dan Williams <dan.j.williams@intel.com>
Date: Tue Jan 2 11:10:43 2007 -0700
ARM: Add drivers/dma to arch/arm/Kconfig
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
commit dd2780e949870c341ffb058c60cb05c43fa9df01
Author: Dan Williams <dan.j.williams@intel.com>
Date: Tue Jan 2 11:10:43 2007 -0700
dmaengine: add base support for the async_tx api
The async_tx api provides methods for describing a chain of asynchronous
bulk memory transfers/transforms with support for inter-transactional
dependencies. It is implemented as a dmaengine client
that smooths over the details of different hardware offload engine
implementations. Code that is written to the api can optimize for
asynchrnous operation and the api will fit the chain of operations to the
available offload resources.
Currently the raid5 implementation in the MD raid456 driver has been
converted to the async_tx api. A driver for the offload engines on the
Intel Xscale series of I/O processors, iop-adma, is provided. With the
iop-adma driver and async_txi, raid456 is able to offload copy, xor, and
xor-zero-sum operations to hardware engines.
On iop342 tiobench showed higher throughput for sequential writes (20 - 30%
improvement) and sequential reads to a degraded array (40 - 55%
improvement). For the other cases performance was roughly equal, +/- a few
percentage points. On a x86-smp platform the performance of the async_tx
implementation (in synchronous mode) was also +/- a few percentage points
of the original implementation. According to 'top' CPU utilization was
positively affected in the offload case, but exact measurements have yet to
be taken.
The tiobench command line used for testing was:
tiobench --size 2048 --block 4096 --block 131072 --dir /mnt/raid --numruns 5
* iop342 had 1GB of memory available
This patch:
1/ introduces struct dma_async_tx_descriptor as a common field for all dmaengine
software descriptors
2/ converts the device_memcpy_* methods into separate prep, set src/dest, and
submit stages
3/ adds support for capabilities beyond memcpy (xor, memset, xor zero sum, completion
interrupts)
4/ converts ioatdma to the new semantics
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
commit 9cca4c035b62b2246f7b17526fede21478610aed
Author: David Brownell <david-b@pacbell.net>
Date: Fri Feb 9 17:47:44 2007 -0700
rm pointless dmaengine exports
This removes several pointless exports from drivers/dma/dmaengine.c;
the dma_async_memcpy_*() functions are inlined by <linux/dmaengine.h>
so those exports are inappropriate.
It also moves the existing EXPORT_SYMBOL declarations next to their
functions, so it's now trivial to confirm one-to-one correspondence
between exports and nonstatic symbols.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
commit 488de00e75000916f43fcbd5572144141d9780fb
Author: Dan Williams <dan.j.williams@intel.com>
Date: Tue Jan 2 11:10:43 2007 -0700
ARM: allow DMA_NONE in consistent_sync
Let applications, that know the state of their buffers, skip cache
maintenance operations.
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
commit adc8fdae82701ad7017cf50099ae7912413f1cdb
Author: Dan Williams <dan.j.williams@intel.com>
Date: Tue Jan 2 11:10:43 2007 -0700
iop3xx: Give Linux control over PCI (ATU) initialization
Currently the iop3xx platform support code assumes that RedBoot is the
bootloader and has already initialized the ATU. Linux should handle this
initialization for three reasons:
1/ The memory map that RedBoot sets up is not optimal (page_to_dma and
virt_to_phys return different addresses). The effect of this is that using
the dma mapping API for the internal bus dma units generates pci bus
addresses that are incorrect for the internal bus.
2/ Not all iop platforms use RedBoot
3/ If the ATU is already initialized it indicates that the iop is an add-in
card in another host, it does not own the PCI bus, and should not be
re-initialized.
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
commit 0d63e839b61be5551f0a53e48f3f3a11e9d8571f
Author: Dan Williams <dan.j.williams@intel.com>
Date: Tue Jan 2 11:10:43 2007 -0700
iop3xx: define IOP3XX_REG_ADDR[32|16|8] and clean up DMA/AAU defs
Also brings the iop3xx registers in line with the format of the iop13xx
register definitions.
Changelog:
* fixed a GPIO register definition error
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
commit 14a58df2c6b26c70d591e122205eb1faf0e38d77
Author: Dan Williams <dan.j.williams@intel.com>
Date: Tue Jan 2 11:10:42 2007 -0700
iop13xx: add resource definitions for the tpmi units
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
commit ffcfe70820db5fea2fcc4f0ba97145afb7da923c
Author: Daniel Wolstenholme <daniel.e.wolstenholme@intel.com>
Date: Tue Jan 2 11:10:42 2007 -0700
iop13xx: msi support
Enable devices to signal interrupts via PCI memory cycles.
Changelog:
* updated for 2.6.19
Signed-off-by: Daniel Wolstenholme <daniel.e.wolstenholme@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
commit dad4e05d802205a6e58a6c434fd1a3fcf255e1c8
Author: Greg Tucker <greg.b.tucker@intel.com>
Date: Tue Jan 2 11:10:42 2007 -0700
iop13xx: imu scsi driver
Enable Linux to access the other core as if it were a scsi target.
Made changes suggested by James Bottomley such as dma_map direction not
bidirectional, proper SCSI return conditons, reset handlers and cleanup.
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
commit cec5e01cd96e3d2065bda6393a0f51d65776c1d7
Author: Greg Tucker <greg.b.tucker@intel.com>
Date: Tue Jan 2 11:10:42 2007 -0700
iop13xx: add base support for the imu
The interprocessor messaging unit supports mailbox style communication
between the two Xscale cores on iop342.
Signed-off-by: Greg Tucker <greg.b.tucker@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
commit 063a2381780ebe3ec73576e068de191b50a17048
Author: Adam Brooks <adam.j.brooks@intel.com>
Date: Tue Jan 2 11:10:41 2007 -0700
iop13xx: clean up xscale oprofile support and add xsc3 support
Signed-off-by: Adam Brooks <adam.j.brooks@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
commit b0c0d7bc2f1417b593786d6f98b5c11a3d665156
Author: Dan Williams <dan.j.williams@intel.com>
Date: Tue Jan 2 11:10:41 2007 -0700
iop: unify time implementation across iop32x, iop33x, and iop13xx
* architecture specific details are handled in asm/arch/time.h
* ARCH_IOP13XX now selects PLAT_IOP
* as suggested by Lennert use ifdef CONFIG_XSCALE to skip the cp_wait on
XSC3
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
commit 4a20027d376dfb567fdd51177082aac028fe5785
Author: Dan Williams <dan.j.williams@intel.com>
Date: Tue Jan 2 11:10:41 2007 -0700
iop: remove cp6_enable/disable routines
This functionality is replaced by cp6_trap
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
commit a855efbd658d931c5e1cd81970266e1aa6b7899d
Author: Dan Williams <dan.j.williams@intel.com>
Date: Tue Jan 2 11:10:40 2007 -0700
entry: introduce get_irqnr_preamble and arch_ret_to_user
get_irqnr_preamble allows machines to take some action before entering the
get_irqnr_and_base loop. On iop we enable cp6 access.
arch_ret_to_user is added to the userspace return path to allow individual
architectures to take actions, like disabling coprocessor access, before
the final return to userspace.
Per Nicolas Pitre's note, there is no need to cp_wait on the return to user
as the latency to return is sufficient.
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
commit 16beeb5f2fa40c4ac6b735c007e29b38f5007b81
Author: Dan Williams <dan.j.williams@intel.com>
Date: Tue Jan 2 11:10:40 2007 -0700
iop: cp6 access handler (undef_hook)
Enable svc access to cp6 via an undefined instruction hook. Do not enable
access for usr code.
This patch also makes iop13xx select PLAT_IOP, this requires a small change
to drivers/i2c/busses/i2c-iop3xx.c.
Per Lennert Buytenhek's note, the cp6 trap routine is moved to arch/arm/plat-iop
Per Nicolas Pitre's note, the cp_wait is skipped since the latency to
return to the faulting function is longer than cp_wait.
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
commit bb595578f2fcd545efdde8fc281495680e36a712
Author: Dan Williams <dan.j.williams@intel.com>
Date: Tue Jan 2 11:10:40 2007 -0700
do_undefinstr: read svc undefined instructions with svc privileges
do_undefinstr currently does not expect undefined instructions in kernel
code, since it always uses get_user() to read the instruction.
Dereference the 'pc' pointer directly in the SVC case.
Per Nicolas Pitre's note, kernel code is never in thumb mode.
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
commit 7c416d5964234cd3eeccdec403c809b380281807
Author: Dan Williams <dan.j.williams@intel.com>
Date: Tue Jan 2 11:10:37 2007 -0700
iop3xx: fix the ioremap implementation to not remap static ranges
Implement a custom ioremap implementation for iop3xx. This saves
establishing new mappings. It also cleans up the PCI IO resource to be a
physical address rather than a virtual address as Russell pointed out on
the original iop13xx port.
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
