[87e73d]: src / libxineadec / nosefart / nes6502.c Maximize Restore History

Download this file

nes6502.c    2565 lines (2122 with data), 54.2 kB

   1
   2
   3
   4
   5
   6
   7
   8
   9
  10
  11
  12
  13
  14
  15
  16
  17
  18
  19
  20
  21
  22
  23
  24
  25
  26
  27
  28
  29
  30
  31
  32
  33
  34
  35
  36
  37
  38
  39
  40
  41
  42
  43
  44
  45
  46
  47
  48
  49
  50
  51
  52
  53
  54
  55
  56
  57
  58
  59
  60
  61
  62
  63
  64
  65
  66
  67
  68
  69
  70
  71
  72
  73
  74
  75
  76
  77
  78
  79
  80
  81
  82
  83
  84
  85
  86
  87
  88
  89
  90
  91
  92
  93
  94
  95
  96
  97
  98
  99
 100
 101
 102
 103
 104
 105
 106
 107
 108
 109
 110
 111
 112
 113
 114
 115
 116
 117
 118
 119
 120
 121
 122
 123
 124
 125
 126
 127
 128
 129
 130
 131
 132
 133
 134
 135
 136
 137
 138
 139
 140
 141
 142
 143
 144
 145
 146
 147
 148
 149
 150
 151
 152
 153
 154
 155
 156
 157
 158
 159
 160
 161
 162
 163
 164
 165
 166
 167
 168
 169
 170
 171
 172
 173
 174
 175
 176
 177
 178
 179
 180
 181
 182
 183
 184
 185
 186
 187
 188
 189
 190
 191
 192
 193
 194
 195
 196
 197
 198
 199
 200
 201
 202
 203
 204
 205
 206
 207
 208
 209
 210
 211
 212
 213
 214
 215
 216
 217
 218
 219
 220
 221
 222
 223
 224
 225
 226
 227
 228
 229
 230
 231
 232
 233
 234
 235
 236
 237
 238
 239
 240
 241
 242
 243
 244
 245
 246
 247
 248
 249
 250
 251
 252
 253
 254
 255
 256
 257
 258
 259
 260
 261
 262
 263
 264
 265
 266
 267
 268
 269
 270
 271
 272
 273
 274
 275
 276
 277
 278
 279
 280
 281
 282
 283
 284
 285
 286
 287
 288
 289
 290
 291
 292
 293
 294
 295
 296
 297
 298
 299
 300
 301
 302
 303
 304
 305
 306
 307
 308
 309
 310
 311
 312
 313
 314
 315
 316
 317
 318
 319
 320
 321
 322
 323
 324
 325
 326
 327
 328
 329
 330
 331
 332
 333
 334
 335
 336
 337
 338
 339
 340
 341
 342
 343
 344
 345
 346
 347
 348
 349
 350
 351
 352
 353
 354
 355
 356
 357
 358
 359
 360
 361
 362
 363
 364
 365
 366
 367
 368
 369
 370
 371
 372
 373
 374
 375
 376
 377
 378
 379
 380
 381
 382
 383
 384
 385
 386
 387
 388
 389
 390
 391
 392
 393
 394
 395
 396
 397
 398
 399
 400
 401
 402
 403
 404
 405
 406
 407
 408
 409
 410
 411
 412
 413
 414
 415
 416
 417
 418
 419
 420
 421
 422
 423
 424
 425
 426
 427
 428
 429
 430
 431
 432
 433
 434
 435
 436
 437
 438
 439
 440
 441
 442
 443
 444
 445
 446
 447
 448
 449
 450
 451
 452
 453
 454
 455
 456
 457
 458
 459
 460
 461
 462
 463
 464
 465
 466
 467
 468
 469
 470
 471
 472
 473
 474
 475
 476
 477
 478
 479
 480
 481
 482
 483
 484
 485
 486
 487
 488
 489
 490
 491
 492
 493
 494
 495
 496
 497
 498
 499
 500
 501
 502
 503
 504
 505
 506
 507
 508
 509
 510
 511
 512
 513
 514
 515
 516
 517
 518
 519
 520
 521
 522
 523
 524
 525
 526
 527
 528
 529
 530
 531
 532
 533
 534
 535
 536
 537
 538
 539
 540
 541
 542
 543
 544
 545
 546
 547
 548
 549
 550
 551
 552
 553
 554
 555
 556
 557
 558
 559
 560
 561
 562
 563
 564
 565
 566
 567
 568
 569
 570
 571
 572
 573
 574
 575
 576
 577
 578
 579
 580
 581
 582
 583
 584
 585
 586
 587
 588
 589
 590
 591
 592
 593
 594
 595
 596
 597
 598
 599
 600
 601
 602
 603
 604
 605
 606
 607
 608
 609
 610
 611
 612
 613
 614
 615
 616
 617
 618
 619
 620
 621
 622
 623
 624
 625
 626
 627
 628
 629
 630
 631
 632
 633
 634
 635
 636
 637
 638
 639
 640
 641
 642
 643
 644
 645
 646
 647
 648
 649
 650
 651
 652
 653
 654
 655
 656
 657
 658
 659
 660
 661
 662
 663
 664
 665
 666
 667
 668
 669
 670
 671
 672
 673
 674
 675
 676
 677
 678
 679
 680
 681
 682
 683
 684
 685
 686
 687
 688
 689
 690
 691
 692
 693
 694
 695
 696
 697
 698
 699
 700
 701
 702
 703
 704
 705
 706
 707
 708
 709
 710
 711
 712
 713
 714
 715
 716
 717
 718
 719
 720
 721
 722
 723
 724
 725
 726
 727
 728
 729
 730
 731
 732
 733
 734
 735
 736
 737
 738
 739
 740
 741
 742
 743
 744
 745
 746
 747
 748
 749
 750
 751
 752
 753
 754
 755
 756
 757
 758
 759
 760
 761
 762
 763
 764
 765
 766
 767
 768
 769
 770
 771
 772
 773
 774
 775
 776
 777
 778
 779
 780
 781
 782
 783
 784
 785
 786
 787
 788
 789
 790
 791
 792
 793
 794
 795
 796
 797
 798
 799
 800
 801
 802
 803
 804
 805
 806
 807
 808
 809
 810
 811
 812
 813
 814
 815
 816
 817
 818
 819
 820
 821
 822
 823
 824
 825
 826
 827
 828
 829
 830
 831
 832
 833
 834
 835
 836
 837
 838
 839
 840
 841
 842
 843
 844
 845
 846
 847
 848
 849
 850
 851
 852
 853
 854
 855
 856
 857
 858
 859
 860
 861
 862
 863
 864
 865
 866
 867
 868
 869
 870
 871
 872
 873
 874
 875
 876
 877
 878
 879
 880
 881
 882
 883
 884
 885
 886
 887
 888
 889
 890
 891
 892
 893
 894
 895
 896
 897
 898
 899
 900
 901
 902
 903
 904
 905
 906
 907
 908
 909
 910
 911
 912
 913
 914
 915
 916
 917
 918
 919
 920
 921
 922
 923
 924
 925
 926
 927
 928
 929
 930
 931
 932
 933
 934
 935
 936
 937
 938
 939
 940
 941
 942
 943
 944
 945
 946
 947
 948
 949
 950
 951
 952
 953
 954
 955
 956
 957
 958
 959
 960
 961
 962
 963
 964
 965
 966
 967
 968
 969
 970
 971
 972
 973
 974
 975
 976
 977
 978
 979
 980
 981
 982
 983
 984
 985
 986
 987
 988
 989
 990
 991
 992
 993
 994
 995
 996
 997
 998
 999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
/*
** Nofrendo (c) 1998-2000 Matthew Conte (matt@conte.com)
**
**
** This program is free software; you can redistribute it and/or
** modify it under the terms of version 2 of the GNU Library General
** Public License as published by the Free Software Foundation.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
** Library General Public License for more details. To obtain a
** copy of the GNU Library General Public License, write to the Free
** Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
**
** Any permitted reproduction of these routines, in whole or in part,
** must bear this legend.
**
**
** nes6502.c
**
** NES custom 6502 (2A03) CPU implementation
** $Id: nes6502.c,v 1.2 2003/01/09 19:50:03 jkeil Exp $
*/
#include "types.h"
#include "nes6502.h"
#include "dis6502.h"
#include <stdio.h>
#define ADD_CYCLES(x) instruction_cycles += (x)
#define INC_CYCLES() instruction_cycles++
//#define ADD_CYCLES(x) remaining_cycles -= (x)
//#define INC_CYCLES() remaining_cycles--
/*
** Check to see if an index reg addition overflowed to next page
*/
#define CHECK_INDEX_OVERFLOW(addr, reg) \
{ \
if ((uint8) (addr) < (reg)) \
INC_CYCLES(); \
}
/*
** Addressing mode macros
*/
#define NO_READ(value) /* empty */
#define IMMEDIATE_BYTE(value) \
{ \
value = bank_readbyte(PC++); \
}
#define ABSOLUTE_ADDR(address) \
{ \
address = bank_readaddress(PC); \
PC += 2; \
}
#define ABSOLUTE(address, value) \
{ \
ABSOLUTE_ADDR(address); \
value = mem_read(address); \
}
#define ABSOLUTE_BYTE(value) \
{ \
ABSOLUTE(temp, value); \
}
#define ABS_IND_X_ADDR(address) \
{ \
address = (bank_readaddress(PC) + X) & 0xFFFF; \
PC += 2; \
CHECK_INDEX_OVERFLOW(address, X); \
}
#define ABS_IND_X(address, value) \
{ \
ABS_IND_X_ADDR(address); \
value = mem_read(address); \
}
#define ABS_IND_X_BYTE(value) \
{ \
ABS_IND_X(temp, value); \
}
#define ABS_IND_Y_ADDR(address) \
{ \
address = (bank_readaddress(PC) + Y) & 0xFFFF; \
PC += 2; \
CHECK_INDEX_OVERFLOW(address, Y); \
}
#define ABS_IND_Y(address, value) \
{ \
ABS_IND_Y_ADDR(address); \
value = mem_read(address); \
}
#define ABS_IND_Y_BYTE(value) \
{ \
ABS_IND_Y(temp, value); \
}
#define ZERO_PAGE_ADDR(address) \
{ \
IMMEDIATE_BYTE(address); \
}
#define ZERO_PAGE(address, value) \
{ \
ZERO_PAGE_ADDR(address); \
value = ZP_READ(address); \
}
#define ZERO_PAGE_BYTE(value) \
{ \
ZERO_PAGE(btemp, value); \
}
/* Zero-page indexed Y doesn't really exist, just for LDX / STX */
#define ZP_IND_X_ADDR(address) \
{ \
address = bank_readbyte(PC++) + X; \
}
#define ZP_IND_X(bAddr, value) \
{ \
ZP_IND_X_ADDR(bAddr); \
value = ZP_READ(bAddr); \
}
#define ZP_IND_X_BYTE(value) \
{ \
ZP_IND_X(btemp, value); \
}
#define ZP_IND_Y_ADDR(address) \
{ \
address = bank_readbyte(PC++) + Y; \
}
#define ZP_IND_Y(address, value) \
{ \
ZP_IND_Y_ADDR(address); \
value = ZP_READ(address); \
}
#define ZP_IND_Y_BYTE(value) \
{ \
ZP_IND_Y(btemp, value); \
}
/*
** For conditional jump relative instructions
** (BCC, BCS, BEQ, BMI, BNE, BPL, BVC, BVS)
*/
#define RELATIVE_JUMP(cond) \
{ \
if (cond) \
{ \
IMMEDIATE_BYTE(btemp); \
if (((int8) btemp + (uint8) PC) & 0xFF00) \
ADD_CYCLES(4); \
else \
ADD_CYCLES(3); \
PC += ((int8) btemp); \
} \
else \
{ \
PC++; \
ADD_CYCLES(2); \
} \
}
/*
** This is actually indexed indirect, but I call it
** indirect X to avoid confusion
*/
#define INDIR_X_ADDR(address) \
{ \
btemp = bank_readbyte(PC++) + X; \
address = zp_address(btemp); \
}
#define INDIR_X(address, value) \
{ \
INDIR_X_ADDR(address); \
value = mem_read(address); \
}
#define INDIR_X_BYTE(value) \
{ \
INDIR_X(temp, value); \
}
/*
** This is actually indirect indexed, but I call it
** indirect y to avoid confusion
*/
#define INDIR_Y_ADDR(address) \
{ \
IMMEDIATE_BYTE(btemp); \
address = (zp_address(btemp) + Y) & 0xFFFF; \
/* ???? */ \
CHECK_INDEX_OVERFLOW(address, Y); \
}
#define INDIR_Y(address, value) \
{ \
INDIR_Y_ADDR(address); \
value = mem_read(address); \
}
#define INDIR_Y_BYTE(value) \
{ \
/*IMMEDIATE_BYTE(btemp); \
temp = zp_address(btemp) + Y; \
CHECK_INDEX_OVERFLOW(temp, Y); \
value = mem_read(temp);*/ \
INDIR_Y(temp, value); \
}
#define JUMP(address) PC = bank_readaddress((address))
/*
** Interrupt macros
*/
#define NMI() \
{ \
PUSH(PC >> 8); \
PUSH(PC & 0xFF); \
CLEAR_FLAG(B_FLAG); \
PUSH(P); \
SET_FLAG(I_FLAG); \
JUMP(NMI_VECTOR); \
int_pending &= ~NMI_MASK; \
ADD_CYCLES(INT_CYCLES); \
}
#define IRQ() \
{ \
PUSH(PC >> 8); \
PUSH(PC & 0xFF); \
CLEAR_FLAG(B_FLAG); \
PUSH(P); \
SET_FLAG(I_FLAG); \
JUMP(IRQ_VECTOR); \
int_pending &= ~IRQ_MASK; \
ADD_CYCLES(INT_CYCLES); \
}
/*
** Instruction macros
*/
/* Warning! NES CPU has no decimal mode, so by default this does no BCD! */
#ifdef NES6502_DECIMAL
#define ADC(cycles, read_func) \
{ \
read_func(data); \
if (P & D_FLAG) \
{ \
temp = (A & 0x0F) + (data & 0x0F) + (P & C_FLAG); \
if (temp >= 10) \
temp = (temp - 10) | 0x10; \
temp += (A & 0xF0) + (data & 0xF0); \
TEST_AND_FLAG(0 == ((A + data + (P & C_FLAG)) & 0xFF), Z_FLAG); \
TEST_AND_FLAG(temp & 0x80, N_FLAG); \
TEST_AND_FLAG(((~(A ^ data)) & (A ^ temp) & 0x80), V_FLAG); \
if (temp > 0x9F) \
temp += 0x60; \
TEST_AND_FLAG(temp > 0xFF, C_FLAG); \
A = (uint8) temp; \
} \
else \
{ \
temp = A + data + (P & C_FLAG); \
/* Set C on carry */ \
TEST_AND_FLAG(temp > 0xFF, C_FLAG); \
/* Set V on overflow */ \
TEST_AND_FLAG(((~(A ^ data)) & (A ^ temp) & 0x80), V_FLAG); \
A = (uint8) temp; \
SET_NZ_FLAGS(A); \
}\
ADD_CYCLES(cycles); \
}
#else
#define ADC(cycles, read_func) \
{ \
read_func(data); \
temp = A + data + (P & C_FLAG); \
/* Set C on carry */ \
TEST_AND_FLAG(temp > 0xFF, C_FLAG); \
/* Set V on overflow */ \
TEST_AND_FLAG(((~(A ^ data)) & (A ^ temp) & 0x80), V_FLAG); \
A = (uint8) temp; \
SET_NZ_FLAGS(A); \
ADD_CYCLES(cycles); \
}
#endif /* NES6502_DECIMAL */
/* undocumented */
#define ANC(cycles, read_func) \
{ \
read_func(data); \
A &= data; \
SET_NZ_FLAGS(A); \
TEST_AND_FLAG(P & N_FLAG, C_FLAG); \
ADD_CYCLES(cycles); \
}
#define AND(cycles, read_func) \
{ \
read_func(data); \
A &= data; \
SET_NZ_FLAGS(A); \
ADD_CYCLES(cycles); \
}
/* undocumented */
#define ANE(cycles, read_func) \
{ \
read_func(data); \
A = (A | 0xEE) & X & data; \
SET_NZ_FLAGS(A); \
ADD_CYCLES(cycles); \
}
/* undocumented */
#ifdef NES6502_DECIMAL
#define ARR(cycles, read_func) \
{ \
read_func(data); \
data &= A; \
if (P & D_FLAG) \
{ \
temp = (data >> 1) | ((P & C_FLAG) << 7); \
SET_NZ_FLAGS(temp); \
TEST_AND_FLAG((temp ^ data) & 0x40, V_FLAG); \
if (((data & 0x0F) + (data & 0x01)) > 5) \
temp = (temp & 0xF0) | ((temp + 0x6) & 0x0F); \
if (((data & 0xF0) + (data & 0x10)) > 0x50) \
{ \
temp = (temp & 0x0F) | ((temp + 0x60) & 0xF0); \
SET_FLAG(C_FLAG); \
} \
else \
CLEAR_FLAG(C_FLAG); \
A = (uint8) temp; \
} \
else \
{ \
A = (data >> 1) | ((P & C_FLAG) << 7); \
SET_NZ_FLAGS(A); \
TEST_AND_FLAG(A & 0x40, C_FLAG); \
TEST_AND_FLAG(((A >> 6) ^ (A >> 5)) & 1, V_FLAG); \
}\
ADD_CYCLES(cycles); \
}
#else
#define ARR(cycles, read_func) \
{ \
read_func(data); \
data &= A; \
A = (data >> 1) | ((P & C_FLAG) << 7); \
SET_NZ_FLAGS(A); \
TEST_AND_FLAG(A & 0x40, C_FLAG); \
TEST_AND_FLAG((A >> 6) ^ (A >> 5), V_FLAG); \
ADD_CYCLES(cycles); \
}
#endif /* NES6502_DECIMAL */
#define ASL(cycles, read_func, write_func, addr) \
{ \
read_func(addr, data); \
TEST_AND_FLAG(data & 0x80, C_FLAG); \
data <<= 1; \
write_func(addr, data); \
SET_NZ_FLAGS(data); \
ADD_CYCLES(cycles); \
}
#define ASL_A() \
{ \
TEST_AND_FLAG(A & 0x80, C_FLAG); \
A <<= 1; \
SET_NZ_FLAGS(A); \
ADD_CYCLES(2); \
}
/* undocumented */
#define ASR(cycles, read_func) \
{ \
read_func(data); \
data &= A; \
TEST_AND_FLAG(data & 0x01, C_FLAG); \
A = data >> 1; \
SET_NZ_FLAGS(A); \
ADD_CYCLES(cycles); \
}
#define BCC() \
{ \
RELATIVE_JUMP((IS_FLAG_CLEAR(C_FLAG))); \
}
#define BCS() \
{ \
RELATIVE_JUMP((IS_FLAG_SET(C_FLAG))); \
}
#define BEQ() \
{ \
RELATIVE_JUMP((IS_FLAG_SET(Z_FLAG))); \
}
#define BIT(cycles, read_func) \
{ \
read_func(data); \
TEST_AND_FLAG(0 == (data & A), Z_FLAG);\
CLEAR_FLAG(N_FLAG | V_FLAG); \
/* move bit 7/6 of data into N/V flags */ \
SET_FLAG(data & (N_FLAG | V_FLAG)); \
ADD_CYCLES(cycles); \
}
#define BMI() \
{ \
RELATIVE_JUMP((IS_FLAG_SET(N_FLAG))); \
}
#define BNE() \
{ \
RELATIVE_JUMP((IS_FLAG_CLEAR(Z_FLAG))); \
}
#define BPL() \
{ \
RELATIVE_JUMP((IS_FLAG_CLEAR(N_FLAG))); \
}
/* Software interrupt type thang */
#define BRK() \
{ \
PC++; \
PUSH(PC >> 8); \
PUSH(PC & 0xFF); \
SET_FLAG(B_FLAG); \
PUSH(P); \
SET_FLAG(I_FLAG); \
JUMP(IRQ_VECTOR); \
ADD_CYCLES(7); \
}
#define BVC() \
{ \
RELATIVE_JUMP((IS_FLAG_CLEAR(V_FLAG))); \
}
#define BVS() \
{ \
RELATIVE_JUMP((IS_FLAG_SET(V_FLAG))); \
}
#define CLC() \
{ \
CLEAR_FLAG(C_FLAG); \
ADD_CYCLES(2); \
}
#define CLD() \
{ \
CLEAR_FLAG(D_FLAG); \
ADD_CYCLES(2); \
}
#define CLI() \
{ \
CLEAR_FLAG(I_FLAG); \
ADD_CYCLES(2); \
}
#define CLV() \
{ \
CLEAR_FLAG(V_FLAG); \
ADD_CYCLES(2); \
}
/* TODO: ick! */
#define _COMPARE(reg, value) \
{ \
temp = (reg) - (value); \
/* C is clear when data > A */ \
TEST_AND_FLAG(0 == (temp & 0x8000), C_FLAG); \
SET_NZ_FLAGS((uint8) temp); /* handles Z flag */ \
}
#define CMP(cycles, read_func) \
{ \
read_func(data); \
_COMPARE(A, data); \
ADD_CYCLES(cycles); \
}
#define CPX(cycles, read_func) \
{ \
read_func(data); \
_COMPARE(X, data); \
ADD_CYCLES(cycles); \
}
#define CPY(cycles, read_func) \
{ \
read_func(data); \
_COMPARE(Y, data); \
ADD_CYCLES(cycles); \
}
/* undocumented */
#define DCP(cycles, read_func, write_func, addr) \
{ \
read_func(addr, data); \
data--; \
write_func(addr, data); \
CMP(cycles, NO_READ); \
}
#define DEC(cycles, read_func, write_func, addr) \
{ \
read_func(addr, data); \
data--; \
write_func(addr, data); \
SET_NZ_FLAGS(data); \
ADD_CYCLES(cycles); \
}
#define DEX() \
{ \
X--; \
SET_NZ_FLAGS(X); \
ADD_CYCLES(2); \
}
#define DEY() \
{ \
Y--; \
SET_NZ_FLAGS(Y); \
ADD_CYCLES(2); \
}
/* undocumented (double-NOP) */
#define DOP(cycles) \
{ \
PC++; \
ADD_CYCLES(cycles); \
}
#define EOR(cycles, read_func) \
{ \
read_func(data); \
A ^= data; \
SET_NZ_FLAGS(A); \
ADD_CYCLES(cycles); \
}
#define INC(cycles, read_func, write_func, addr) \
{ \
read_func(addr, data); \
data++; \
write_func(addr, data); \
SET_NZ_FLAGS(data); \
ADD_CYCLES(cycles); \
}
#define INX() \
{ \
X++; \
SET_NZ_FLAGS(X); \
ADD_CYCLES(2); \
}
#define INY() \
{ \
Y++; \
SET_NZ_FLAGS(Y); \
ADD_CYCLES(2); \
}
/* undocumented */
#define ISB(cycles, read_func, write_func, addr) \
{ \
read_func(addr, data); \
data++; \
write_func(addr, data); \
SBC(cycles, NO_READ); \
}
#ifdef NES6502_TESTOPS
#define JAM() \
{ \
cpu_Jam(); \
}
#elif defined(NSF_PLAYER)
#define JAM() \
{ \
}
#else
#define JAM() \
{ \
char jambuf[20]; \
sprintf(jambuf, "JAM: PC=$%04X", PC); \
ASSERT_MSG(jambuf); \
ADD_CYCLES(2); \
}
#endif /* NES6502_TESTOPS */
#define JMP_INDIRECT() \
{ \
temp = bank_readaddress(PC); \
/* bug in crossing page boundaries */ \
if (0xFF == (uint8) temp) \
PC = (bank_readbyte(temp & ~0xFF) << 8) | bank_readbyte(temp); \
else \
JUMP(temp); \
ADD_CYCLES(5); \
}
#define JMP_ABSOLUTE() \
{ \
JUMP(PC); \
ADD_CYCLES(3); \
}
#define JSR() \
{ \
PC++; \
PUSH(PC >> 8); \
PUSH(PC & 0xFF); \
JUMP(PC - 1); \
ADD_CYCLES(6); \
}
/* undocumented */
#define LAS(cycles, read_func) \
{ \
read_func(data); \
A = X = S = (S & data); \
SET_NZ_FLAGS(A); \
ADD_CYCLES(cycles); \
}
/* undocumented */
#define LAX(cycles, read_func) \
{ \
read_func(A); \
X = A; \
SET_NZ_FLAGS(A); \
ADD_CYCLES(cycles); \
}
#define LDA(cycles, read_func) \
{ \
read_func(A); \
SET_NZ_FLAGS(A); \
ADD_CYCLES(cycles); \
}
#define LDX(cycles, read_func) \
{ \
read_func(X); \
SET_NZ_FLAGS(X);\
ADD_CYCLES(cycles); \
}
#define LDY(cycles, read_func) \
{ \
read_func(Y); \
SET_NZ_FLAGS(Y);\
ADD_CYCLES(cycles); \
}
#define LSR(cycles, read_func, write_func, addr) \
{ \
read_func(addr, data); \
TEST_AND_FLAG(data & 0x01, C_FLAG); \
data >>= 1; \
write_func(addr, data); \
SET_NZ_FLAGS(data); \
ADD_CYCLES(cycles); \
}
#define LSR_A() \
{ \
TEST_AND_FLAG(A & 0x01, C_FLAG); \
A >>= 1; \
SET_NZ_FLAGS(A); \
ADD_CYCLES(2); \
}
/* undocumented */
#define LXA(cycles, read_func) \
{ \
read_func(data); \
A = X = ((A | 0xEE) & data); \
SET_NZ_FLAGS(A); \
ADD_CYCLES(cycles); \
}
#define NOP() \
{ \
ADD_CYCLES(2); \
}
#define ORA(cycles, read_func) \
{ \
read_func(data); \
A |= data; \
SET_NZ_FLAGS(A);\
ADD_CYCLES(cycles); \
}
#define PHA() \
{ \
PUSH(A); \
ADD_CYCLES(3); \
}
#define PHP() \
{ \
/* B flag is pushed on stack as well */ \
PUSH((P | B_FLAG)); \
ADD_CYCLES(3); \
}
#define PLA() \
{ \
A = PULL(); \
SET_NZ_FLAGS(A); \
ADD_CYCLES(4); \
}
#define PLP() \
{ \
P = PULL(); \
SET_FLAG(R_FLAG); /* ensure reserved flag is set */ \
ADD_CYCLES(4); \
}
/* undocumented */
#define RLA(cycles, read_func, write_func, addr) \
{ \
read_func(addr, data); \
if (P & C_FLAG) \
{ \
TEST_AND_FLAG(data & 0x80, C_FLAG); \
data = (data << 1) | 1; \
} \
else \
{ \
TEST_AND_FLAG(data & 0x80, C_FLAG); \
data <<= 1; \
} \
write_func(addr, data); \
A &= data; \
SET_NZ_FLAGS(A); \
ADD_CYCLES(cycles); \
}
/* 9-bit rotation (carry flag used for rollover) */
#define ROL(cycles, read_func, write_func, addr) \
{ \
read_func(addr, data); \
if (P & C_FLAG) \
{ \
TEST_AND_FLAG(data & 0x80, C_FLAG); \
data = (data << 1) | 1; \
} \
else \
{ \
TEST_AND_FLAG(data & 0x80, C_FLAG); \
data <<= 1; \
} \
write_func(addr, data); \
SET_NZ_FLAGS(data); \
ADD_CYCLES(cycles); \
}
#define ROL_A() \
{ \
if (P & C_FLAG) \
{ \
TEST_AND_FLAG(A & 0x80, C_FLAG); \
A = (A << 1) | 1; \
} \
else \
{ \
TEST_AND_FLAG(A & 0x80, C_FLAG); \
A <<= 1; \
} \
SET_NZ_FLAGS(A); \
ADD_CYCLES(2); \
}
#define ROR(cycles, read_func, write_func, addr) \
{ \
read_func(addr, data); \
if (P & C_FLAG) \
{ \
TEST_AND_FLAG(data & 1, C_FLAG); \
data = (data >> 1) | 0x80; \
} \
else \
{ \
TEST_AND_FLAG(data & 1, C_FLAG); \
data >>= 1; \
} \
write_func(addr, data); \
SET_NZ_FLAGS(data); \
ADD_CYCLES(cycles); \
}
#define ROR_A() \
{ \
if (P & C_FLAG) \
{ \
TEST_AND_FLAG(A & 1, C_FLAG); \
A = (A >> 1) | 0x80; \
} \
else \
{ \
TEST_AND_FLAG(A & 1, C_FLAG); \
A >>= 1; \
} \
SET_NZ_FLAGS(A); \
ADD_CYCLES(2); \
}
/* undocumented */
#define RRA(cycles, read_func, write_func, addr) \
{ \
read_func(addr, data); \
if (P & C_FLAG) \
{ \
TEST_AND_FLAG(data & 1, C_FLAG); \
data = (data >> 1) | 0x80; \
} \
else \
{ \
TEST_AND_FLAG(data & 1, C_FLAG); \
data >>= 1; \
} \
write_func(addr, data); \
ADC(cycles, NO_READ); \
}
#define RTI() \
{ \
P = PULL(); \
SET_FLAG(R_FLAG); /* ensure reserved flag is set */ \
PC = PULL(); \
PC |= PULL() << 8; \
ADD_CYCLES(6); \
}
#define RTS() \
{ \
PC = PULL(); \
PC = (PC | (PULL() << 8)) + 1; \
ADD_CYCLES(6); \
}
/* undocumented */
#define SAX(cycles, read_func, write_func, addr) \
{ \
read_func(addr); \
data = A & X; \
write_func(addr, data); \
ADD_CYCLES(cycles); \
}
/* Warning! NES CPU has no decimal mode, so by default this does no BCD! */
#ifdef NES6502_DECIMAL
#define SBC(cycles, read_func) \
{ \
read_func(data); \
/* NOT(C) is considered borrow */ \
temp = A - data - ((P & C_FLAG) ^ C_FLAG); \
if (P & D_FLAG) \
{ \
uint8 al, ah; \
al = (A & 0x0F) - (data & 0x0F) - ((P & C_FLAG) ^ C_FLAG); \
ah = (A >> 4) - (data >> 4); \
if (al & 0x10) \
{ \
al -= 6; \
ah--; \
} \
if (ah & 0x10) \
ah -= 6; \
TEST_AND_FLAG(temp < 0x100, C_FLAG); \
TEST_AND_FLAG(((A ^ temp) & 0x80) && ((A ^ data) & 0x80), V_FLAG); \
SET_NZ_FLAGS(temp & 0xFF); \
A = (ah << 4) | (al & 0x0F); \
} \
else \
{ \
TEST_AND_FLAG(((A ^ temp) & 0x80) && ((A ^ data) & 0x80), V_FLAG); \
TEST_AND_FLAG(temp < 0x100, C_FLAG); \
A = (uint8) temp; \
SET_NZ_FLAGS(A & 0xFF); \
} \
ADD_CYCLES(cycles); \
}
#else
#define SBC(cycles, read_func) \
{ \
read_func(data); \
temp = A - data - ((P & C_FLAG) ^ C_FLAG); \
TEST_AND_FLAG(((A ^ data) & (A ^ temp) & 0x80), V_FLAG); \
TEST_AND_FLAG(temp < 0x100, C_FLAG); \
A = (uint8) temp; \
SET_NZ_FLAGS(A); \
ADD_CYCLES(cycles); \
}
#endif /* NES6502_DECIMAL */
/* undocumented */
#define SBX(cycles, read_func) \
{ \
read_func(data); \
temp = (A & X) - data; \
TEST_AND_FLAG(temp < 0x100, C_FLAG); \
X = temp & 0xFF; \
SET_NZ_FLAGS(X); \
ADD_CYCLES(cycles); \
}
#define SEC() \
{ \
SET_FLAG(C_FLAG); \
ADD_CYCLES(2); \
}
#define SED() \
{ \
SET_FLAG(D_FLAG); \
ADD_CYCLES(2); \
}
#define SEI() \
{ \
SET_FLAG(I_FLAG); \
ADD_CYCLES(2); \
}
/* undocumented */
#define SHA(cycles, read_func, write_func, addr) \
{ \
read_func(addr); \
data = A & X & ((uint8) ((addr >> 8) + 1)); \
write_func(addr, data); \
ADD_CYCLES(cycles); \
}
/* undocumented */
#define SHS(cycles, read_func, write_func, addr) \
{ \
read_func(addr); \
S = A & X; \
data = S & ((uint8) ((addr >> 8) + 1)); \
write_func(addr, data); \
ADD_CYCLES(cycles); \
}
/* undocumented */
#define SHX(cycles, read_func, write_func, addr) \
{ \
read_func(addr); \
data = X & ((uint8) ((addr >> 8) + 1)); \
write_func(addr, data); \
ADD_CYCLES(cycles); \
}
/* undocumented */
#define SHY(cycles, read_func, write_func, addr) \
{ \
read_func(addr); \
data = Y & ((uint8) ((addr >> 8 ) + 1)); \
write_func(addr, data); \
ADD_CYCLES(cycles); \
}
/* undocumented */
#define SLO(cycles, read_func, write_func, addr) \
{ \
read_func(addr, data); \
TEST_AND_FLAG(data & 0x80, C_FLAG); \
data <<= 1; \
write_func(addr, data); \
A |= data; \
SET_NZ_FLAGS(A); \
ADD_CYCLES(cycles); \
}
/* unoffical */
#define SRE(cycles, read_func, write_func, addr) \
{ \
read_func(addr, data); \
TEST_AND_FLAG(data & 1, C_FLAG); \
data >>= 1; \
write_func(addr, data); \
A ^= data; \
SET_NZ_FLAGS(A); \
ADD_CYCLES(cycles); \
}
#define STA(cycles, read_func, write_func, addr) \
{ \
read_func(addr); \
write_func(addr, A); \
ADD_CYCLES(cycles); \
}
#define STX(cycles, read_func, write_func, addr) \
{ \
read_func(addr); \
write_func(addr, X); \
ADD_CYCLES(cycles); \
}
#define STY(cycles, read_func, write_func, addr) \
{ \
read_func(addr); \
write_func(addr, Y); \
ADD_CYCLES(cycles); \
}
#define TAX() \
{ \
X = A; \
SET_NZ_FLAGS(X);\
ADD_CYCLES(2); \
}
#define TAY() \
{ \
Y = A; \
SET_NZ_FLAGS(Y);\
ADD_CYCLES(2); \
}
/* undocumented (triple-NOP) */
#define TOP() \
{ \
PC += 2; \
ADD_CYCLES(4); \
}
#define TSX() \
{ \
X = S; \
SET_NZ_FLAGS(X);\
ADD_CYCLES(2); \
}
#define TXA() \
{ \
A = X; \
SET_NZ_FLAGS(A);\
ADD_CYCLES(2); \
}
#define TXS() \
{ \
S = X; \
ADD_CYCLES(2); \
}
#define TYA() \
{ \
A = Y; \
SET_NZ_FLAGS(A); \
ADD_CYCLES(2); \
}
/*
** Stack and data fetching macros
*/
/* Set/clear/test bits in the flags register */
#define SET_FLAG(mask) P |= (mask)
#define CLEAR_FLAG(mask) P &= ~(mask)
#define IS_FLAG_SET(mask) (P & (mask))
#define IS_FLAG_CLEAR(mask) (0 == IS_FLAG_SET((mask)))
#define TEST_AND_FLAG(test, mask) \
{ \
if ((test)) \
SET_FLAG((mask)); \
else \
CLEAR_FLAG((mask)); \
}
/*
** flag register helper macros
*/
/* register push/pull */
#ifdef NES6502_MEM_ACCESS_CTRL
# define PUSH(value) stack_push((S--),(value))
# define PULL() stack_pull((++S))
#else
# define PUSH(value) stack_page[S--] = (uint8) (value)
# define PULL() stack_page[++S]
#endif /* #ifdef NES6502_MEM_ACCESS_CTRL */
/* Sets the Z and N flags based on given data, taken from precomputed table */
#define SET_NZ_FLAGS(value) P &= ~(N_FLAG | Z_FLAG); \
P |= flag_table[(value)]
#define GET_GLOBAL_REGS() \
{ \
PC = reg_PC; \
A = reg_A; \
X = reg_X; \
Y = reg_Y; \
P = reg_P; \
S = reg_S; \
}
#define SET_LOCAL_REGS() \
{ \
reg_PC = PC; \
reg_A = A; \
reg_X = X; \
reg_Y = Y; \
reg_P = P; \
reg_S = S; \
}
/* static data */
static nes6502_memread *pmem_read, *pmr;
static nes6502_memwrite *pmem_write, *pmw;
/* lookup table for N/Z flags */
static uint8 flag_table[256];
/* internal critical CPU vars */
static uint32 reg_PC;
static uint8 reg_A, reg_P, reg_X, reg_Y, reg_S;
static uint8 int_pending;
static int dma_cycles;
/* execution cycle count (can be reset by user) */
static uint32 total_cycles = 0;
/* memory region pointers */
static uint8 *nes6502_banks[NES6502_NUMBANKS];
static uint8 *ram = NULL;
static uint8 *stack_page = NULL;
/* access flag for memory
* $$$ ben : I add this for the playing time calculation.
* Only if compiled with NES6502_MEM_ACCESS.
*/
#ifdef NES6502_MEM_ACCESS_CTRL
uint8 *acc_nes6502_banks[NES6502_NUMBANKS];
static uint8 *acc_ram = NULL;
static uint8 *acc_stack_page = NULL;
uint8 nes6502_mem_access = 0;
/* $$$ ben :
* Set memory access check flags, and store ORed frame global check
* for music time calculation.
*/
static void chk_mem_access(uint8 * access, int flags)
{
uint8 oldchk = * access;
if ((oldchk&flags) != flags) {
nes6502_mem_access |= flags;
*access = oldchk|flags;
}
}
INLINE void stack_push(uint8 s, uint8 v)
{
chk_mem_access(acc_stack_page+s, NES6502_WRITE_ACCESS);
stack_page[s] = v;
}
INLINE uint8 stack_pull(uint8 s)
{
chk_mem_access(acc_stack_page+s, NES6502_READ_ACCESS);
return stack_page[s];
}
INLINE uint8 zp_read(register uint32 addr)
{
chk_mem_access(acc_ram+addr, NES6502_READ_ACCESS);
return ram[addr];
}
INLINE void zp_write(register uint32 addr, uint8 v)
{
chk_mem_access(acc_ram+addr, NES6502_WRITE_ACCESS);
ram[addr] = v;
}
#define ZP_READ(addr) zp_read((addr))
#define ZP_WRITE(addr, value) zp_write((addr),(value))
#define bank_readbyte(address) _bank_readbyte((address), NES6502_READ_ACCESS)
#define bank_readbyte_pc(address) _bank_readbyte((address), NES6502_EXE_ACCESS)
#else
# define chk_mem_access(access, flags)
/*
** Zero-page helper macros
*/
#define ZP_READ(addr) ram[(addr)]
#define ZP_WRITE(addr, value) ram[(addr)] = (uint8) (value)
#define bank_readbyte(address) _bank_readbyte((address))
#define bank_readbyte_pc(address) _bank_readbyte((address))
#endif /* #ifdef NES6502_MEM_ACCESS_CTRL */
#ifdef NES6502_MEM_ACCESS_CTRL
int max_access[NES6502_NUMBANKS] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
INLINE uint8 _bank_readbyte(register uint32 address, const uint8 flags)
#else
INLINE uint8 _bank_readbyte(register uint32 address)
#endif
{
ASSERT(nes6502_banks[address >> NES6502_BANKSHIFT]);
#ifdef NES6502_MEM_ACCESS_CTRL
//printf("chk_mem_access(acc_nes6502_banks[%d] + %d, %d)\n", address>>NES6502_BANKSHIFT, address & NES6502_BANKMASK, flags);
if((address & NES6502_BANKMASK) > max_access[address>>NES6502_BANKSHIFT])
{
max_access[address>>NES6502_BANKSHIFT] = address & NES6502_BANKMASK;
//printf("max_access[%d] increased to %d\n", address>>NES6502_BANKSHIFT, max_access[address>>NES6502_BANKSHIFT]);
}
#endif
chk_mem_access(acc_nes6502_banks[address>>NES6502_BANKSHIFT]
+ (address & NES6502_BANKMASK),
flags);
return nes6502_banks[address >> NES6502_BANKSHIFT][address & NES6502_BANKMASK];
}
INLINE void bank_writebyte(register uint32 address, register uint8 value)
{
ASSERT(nes6502_banks[address >> NES6502_BANKSHIFT]);
#ifdef NES6502_MEM_ACCESS_CTRL
//printf("chk_mem_access(acc_nes6502_banks[%d] + %d, %d)\n", address>>NES6502_BANKSHIFT, address & NES6502_BANKMASK, NES6502_WRITE_ACCESS);
if((address & NES6502_BANKMASK) > max_access[address>>NES6502_BANKSHIFT])
{
max_access[address>>NES6502_BANKSHIFT] = address & NES6502_BANKMASK;
//printf("max_access[%d] increased to %d\n", address>>NES6502_BANKSHIFT, max_access[address>>NES6502_BANKSHIFT]);
}
#endif
chk_mem_access(acc_nes6502_banks[address>>NES6502_BANKSHIFT]
+ (address & NES6502_BANKMASK),
NES6502_WRITE_ACCESS);
nes6502_banks[address >> NES6502_BANKSHIFT][address & NES6502_BANKMASK] = value;
}
/* Read a 16bit word */
#define READ_SNES_16(bank,offset) \
(\
(offset) [ (uint8 *) (bank) ] |\
((unsigned int)( ((offset)+1) [ (uint8 *) (bank) ] ) << 8)\
)
INLINE uint32 zp_address(register uint8 address)
{
chk_mem_access(acc_ram+address, NES6502_READ_ACCESS);
chk_mem_access(acc_ram+address+1, NES6502_READ_ACCESS);
#if defined (HOST_LITTLE_ENDIAN) && defined(HOST_UNALIGN_WORD)
/* TODO: this fails if src address is $xFFF */
/* TODO: this fails if host architecture doesn't support byte alignment */
/* $$$ ben : DONE */
return (uint32) (*(uint16 *)(ram + address));
#elif defined(TARGET_CPU_PPC)
return __lhbrx(ram, address);
#else
return READ_SNES_16(ram,address);
/* uint32 x = (uint32) *(uint16 *)(ram + address); */
/* return (x << 8) | (x >> 8); */
//#endif /* TARGET_CPU_PPC */
#endif /* HOST_LITTLE_ENDIAN */
}
INLINE uint32 bank_readaddress(register uint32 address)
{
#ifdef NES6502_MEM_ACCESS_CTRL
{
const unsigned int offset = address & NES6502_BANKMASK;
uint8 * addr = acc_nes6502_banks[address >> NES6502_BANKSHIFT];
chk_mem_access(addr+offset+0, NES6502_READ_ACCESS);
chk_mem_access(addr+offset+1, NES6502_READ_ACCESS);
}
#endif
#if defined (HOST_LITTLE_ENDIAN) && defined(HOST_UNALIGN_WORD)
/* TODO: this fails if src address is $xFFF */
/* TODO: this fails if host architecture doesn't support byte alignment */
/* $$$ ben : DONE */
return (uint32) (*(uint16 *)(nes6502_banks[address >> NES6502_BANKSHIFT] + (address & NES6502_BANKMASK)));
#elif defined(TARGET_CPU_PPC)
return __lhbrx(nes6502_banks[address >> NES6502_BANKSHIFT], address & NES6502_BANKMASK);
#else
{
const unsigned int offset = address & NES6502_BANKMASK;
return READ_SNES_16(nes6502_banks[address >> NES6502_BANKSHIFT], offset);
}
/* uint32 x = (uint32) *(uint16 *)(nes6502_banks[address >> NES6502_BANKSHIFT] + (address & NES6502_BANKMASK)); */
/* return (x << 8) | (x >> 8); */
//#endif /* TARGET_CPU_PPC */
#endif /* HOST_LITTLE_ENDIAN */
}
/* read a byte of 6502 memory */
static uint8 mem_read(uint32 address)
{
/* TODO: following cases are N2A03-specific */
/* RAM */
if (address < 0x800) {
chk_mem_access(acc_ram + address, NES6502_READ_ACCESS);
return ram[address];
}
/* always paged memory */
// else if (address >= 0x6000)
else if (address >= 0x8000) {
return bank_readbyte(address);
}
/* check memory range handlers */
else
{
for (pmr = pmem_read; pmr->min_range != 0xFFFFFFFF; pmr++)
{
if ((address >= pmr->min_range) && (address <= pmr->max_range))
return pmr->read_func(address);
}
}
/* return paged memory */
return bank_readbyte(address);
}
/* write a byte of data to 6502 memory */
static void mem_write(uint32 address, uint8 value)
{
/* RAM */
if (address < 0x800)
{
chk_mem_access(acc_ram + address, NES6502_WRITE_ACCESS);
ram[address] = value;
return;
}
/* check memory range handlers */
else
{
for (pmw = pmem_write; pmw->min_range != 0xFFFFFFFF; pmw++)
{
if ((address >= pmw->min_range) && (address <= pmw->max_range))
{
pmw->write_func(address, value);
return;
}
}
}
/* write to paged memory */
bank_writebyte(address, value);
}
/* set the current context */
void nes6502_setcontext(nes6502_context *cpu)
{
int loop;
ASSERT(cpu);
/* Set the page pointers */
for (loop = 0; loop < NES6502_NUMBANKS; loop++) {
nes6502_banks[loop] = cpu->mem_page[loop];
#ifdef NES6502_MEM_ACCESS_CTRL
acc_nes6502_banks[loop] = cpu->acc_mem_page[loop];
#endif
}
ram = nes6502_banks[0]; /* quicker zero-page/RAM references */
stack_page = ram + STACK_OFFSET;
#ifdef NES6502_MEM_ACCESS_CTRL
acc_ram = acc_nes6502_banks[0]; /* quicker zero-page/RAM references */
acc_stack_page = acc_ram + STACK_OFFSET;
#endif
pmem_read = cpu->read_handler;
pmem_write = cpu->write_handler;
reg_PC = cpu->pc_reg;
reg_A = cpu->a_reg;
reg_P = cpu->p_reg;
reg_X = cpu->x_reg;
reg_Y = cpu->y_reg;
reg_S = cpu->s_reg;
int_pending = cpu->int_pending;
dma_cycles = cpu->dma_cycles;
}
/* get the current context */
void nes6502_getcontext(nes6502_context *cpu)
{
int loop;
/* Set the page pointers */
for (loop = 0; loop < NES6502_NUMBANKS; loop++) {
cpu->mem_page[loop] = nes6502_banks[loop];
#ifdef NES6502_MEM_ACCESS_CTRL
cpu->acc_mem_page[loop] = acc_nes6502_banks[loop];
#endif
}
cpu->read_handler = pmem_read;
cpu->write_handler = pmem_write;
cpu->pc_reg = reg_PC;
cpu->a_reg = reg_A;
cpu->p_reg = reg_P;
cpu->x_reg = reg_X;
cpu->y_reg = reg_Y;
cpu->s_reg = reg_S;
cpu->int_pending = int_pending;
cpu->dma_cycles = dma_cycles;
}
/* DMA a byte of data from ROM */
uint8 nes6502_getbyte(uint32 address)
{
return bank_readbyte(address);
}
/* get number of elapsed cycles */
uint32 nes6502_getcycles(boolean reset_flag)
{
uint32 cycles = total_cycles;
if (reset_flag)
total_cycles = 0;
return cycles;
}
/* Execute instructions until count expires
**
** Returns the number of cycles *actually* executed
** (note that this can be from 0-6 cycles more than you wanted)
*/
int nes6502_execute(int remaining_cycles)
{
int instruction_cycles, old_cycles = total_cycles;
uint32 temp, addr; /* for macros */
uint32 PC;
uint8 A, X, Y, P, S;
uint8 opcode, data;
uint8 btemp, baddr; /* for macros */
GET_GLOBAL_REGS();
#ifdef NES6502_MEM_ACCESS_CTRL
/* reset global memory access for this execute loop. */
nes6502_mem_access = 0;
#endif
/* Continue until we run out of cycles */
while (remaining_cycles > 0)
{
instruction_cycles = 0;
/* check for DMA cycle burning */
if (dma_cycles)
{
if (remaining_cycles <= dma_cycles)
{
dma_cycles -= remaining_cycles;
total_cycles += remaining_cycles;
goto _execute_done;
}
else
{
remaining_cycles -= dma_cycles;
total_cycles += dma_cycles;
dma_cycles = 0;
}
}
if (int_pending)
{
/* NMI has highest priority */
if (int_pending & NMI_MASK)
{
NMI();
}
/* IRQ has lowest priority */
else /* if (int_pending & IRQ_MASK) */
{
if (IS_FLAG_CLEAR(I_FLAG))
IRQ();
}
}
/* Fetch instruction */
//nes6502_disasm(PC, P, A, X, Y, S);
opcode = bank_readbyte_pc(PC++);
/* Execute instruction */
switch (opcode)
{
case 0x00: /* BRK */
BRK();
break;
case 0x01: /* ORA ($nn,X) */
ORA(6, INDIR_X_BYTE);
break;
/* JAM */
case 0x02: /* JAM */
case 0x12: /* JAM */
case 0x22: /* JAM */
case 0x32: /* JAM */
case 0x42: /* JAM */
case 0x52: /* JAM */
case 0x62: /* JAM */
case 0x72: /* JAM */
case 0x92: /* JAM */
case 0xB2: /* JAM */
case 0xD2: /* JAM */
case 0xF2: /* JAM */
JAM();
/* kill switch for CPU emulation */
goto _execute_done;
case 0x03: /* SLO ($nn,X) */
SLO(8, INDIR_X, mem_write, addr);
break;
case 0x04: /* NOP $nn */
case 0x44: /* NOP $nn */
case 0x64: /* NOP $nn */
DOP(3);
break;
case 0x05: /* ORA $nn */
ORA(3, ZERO_PAGE_BYTE);
break;
case 0x06: /* ASL $nn */
ASL(5, ZERO_PAGE, ZP_WRITE, baddr);
break;
case 0x07: /* SLO $nn */
SLO(5, ZERO_PAGE, ZP_WRITE, baddr);
break;
case 0x08: /* PHP */
PHP();
break;
case 0x09: /* ORA #$nn */
ORA(2, IMMEDIATE_BYTE);
break;
case 0x0A: /* ASL A */
ASL_A();
break;
case 0x0B: /* ANC #$nn */
ANC(2, IMMEDIATE_BYTE);
break;
case 0x0C: /* NOP $nnnn */
TOP();
break;
case 0x0D: /* ORA $nnnn */
ORA(4, ABSOLUTE_BYTE);
break;
case 0x0E: /* ASL $nnnn */
ASL(6, ABSOLUTE, mem_write, addr);
break;
case 0x0F: /* SLO $nnnn */
SLO(6, ABSOLUTE, mem_write, addr);
break;
case 0x10: /* BPL $nnnn */
BPL();
break;
case 0x11: /* ORA ($nn),Y */
ORA(5, INDIR_Y_BYTE);
break;
case 0x13: /* SLO ($nn),Y */
SLO(8, INDIR_Y, mem_write, addr);
break;
case 0x14: /* NOP $nn,X */
case 0x34: /* NOP */
case 0x54: /* NOP $nn,X */
case 0x74: /* NOP $nn,X */
case 0xD4: /* NOP $nn,X */
case 0xF4: /* NOP ($nn,X) */
DOP(4);
break;
case 0x15: /* ORA $nn,X */
ORA(4, ZP_IND_X_BYTE);
break;
case 0x16: /* ASL $nn,X */
ASL(6, ZP_IND_X, ZP_WRITE, baddr);
break;
case 0x17: /* SLO $nn,X */
SLO(6, ZP_IND_X, ZP_WRITE, baddr);
break;
case 0x18: /* CLC */
CLC();
break;
case 0x19: /* ORA $nnnn,Y */
ORA(4, ABS_IND_Y_BYTE);
break;
case 0x1A: /* NOP */
case 0x3A: /* NOP */
case 0x5A: /* NOP */
case 0x7A: /* NOP */
case 0xDA: /* NOP */
case 0xFA: /* NOP */
NOP();
break;
case 0x1B: /* SLO $nnnn,Y */
SLO(7, ABS_IND_Y, mem_write, addr);
break;
case 0x1C: /* NOP $nnnn,X */
case 0x3C: /* NOP $nnnn,X */
case 0x5C: /* NOP $nnnn,X */
case 0x7C: /* NOP $nnnn,X */
case 0xDC: /* NOP $nnnn,X */
case 0xFC: /* NOP $nnnn,X */
TOP();
break;
case 0x1D: /* ORA $nnnn,X */
ORA(4, ABS_IND_X_BYTE);
break;
case 0x1E: /* ASL $nnnn,X */
ASL(7, ABS_IND_X, mem_write, addr);
break;
case 0x1F: /* SLO $nnnn,X */
SLO(7, ABS_IND_X, mem_write, addr);
break;
case 0x20: /* JSR $nnnn */
JSR();
break;
case 0x21: /* AND ($nn,X) */
AND(6, INDIR_X_BYTE);
break;
case 0x23: /* RLA ($nn,X) */
RLA(8, INDIR_X, mem_write, addr);
break;
case 0x24: /* BIT $nn */
BIT(3, ZERO_PAGE_BYTE);
break;
case 0x25: /* AND $nn */
AND(3, ZERO_PAGE_BYTE);
break;
case 0x26: /* ROL $nn */
ROL(5, ZERO_PAGE, ZP_WRITE, baddr);
break;
case 0x27: /* RLA $nn */
RLA(5, ZERO_PAGE, ZP_WRITE, baddr);
break;
case 0x28: /* PLP */
PLP();
break;
case 0x29: /* AND #$nn */
AND(2, IMMEDIATE_BYTE);
break;
case 0x2A: /* ROL A */
ROL_A();
break;
case 0x2B: /* ANC #$nn */
ANC(2, IMMEDIATE_BYTE);
break;
case 0x2C: /* BIT $nnnn */
BIT(4, ABSOLUTE_BYTE);
break;
case 0x2D: /* AND $nnnn */
AND(4, ABSOLUTE_BYTE);
break;
case 0x2E: /* ROL $nnnn */
ROL(6, ABSOLUTE, mem_write, addr);
break;
case 0x2F: /* RLA $nnnn */
RLA(6, ABSOLUTE, mem_write, addr);
break;
case 0x30: /* BMI $nnnn */
BMI();
break;
case 0x31: /* AND ($nn),Y */
AND(5, INDIR_Y_BYTE);
break;
case 0x33: /* RLA ($nn),Y */
RLA(8, INDIR_Y, mem_write, addr);
break;
case 0x35: /* AND $nn,X */
AND(4, ZP_IND_X_BYTE);
break;
case 0x36: /* ROL $nn,X */
ROL(6, ZP_IND_X, ZP_WRITE, baddr);
break;
case 0x37: /* RLA $nn,X */
RLA(6, ZP_IND_X, ZP_WRITE, baddr);
break;
case 0x38: /* SEC */
SEC();
break;
case 0x39: /* AND $nnnn,Y */
AND(4, ABS_IND_Y_BYTE);
break;
case 0x3B: /* RLA $nnnn,Y */
RLA(7, ABS_IND_Y, mem_write, addr);
break;
case 0x3D: /* AND $nnnn,X */
AND(4, ABS_IND_X_BYTE);
break;
case 0x3E: /* ROL $nnnn,X */
ROL(7, ABS_IND_X, mem_write, addr);
break;
case 0x3F: /* RLA $nnnn,X */
RLA(7, ABS_IND_X, mem_write, addr);
break;
case 0x40: /* RTI */
RTI();
break;
case 0x41: /* EOR ($nn,X) */
EOR(6, INDIR_X_BYTE);
break;
case 0x43: /* SRE ($nn,X) */
SRE(8, INDIR_X, mem_write, addr);
break;
case 0x45: /* EOR $nn */
EOR(3, ZERO_PAGE_BYTE);
break;
case 0x46: /* LSR $nn */
LSR(5, ZERO_PAGE, ZP_WRITE, baddr);
break;
case 0x47: /* SRE $nn */
SRE(5, ZERO_PAGE, ZP_WRITE, baddr);
break;
case 0x48: /* PHA */
PHA();
break;
case 0x49: /* EOR #$nn */
EOR(2, IMMEDIATE_BYTE);
break;
case 0x4A: /* LSR A */
LSR_A();
break;
case 0x4B: /* ASR #$nn */
ASR(2, IMMEDIATE_BYTE);
break;
case 0x4C: /* JMP $nnnn */
JMP_ABSOLUTE();
break;
case 0x4D: /* EOR $nnnn */
EOR(4, ABSOLUTE_BYTE);
break;
case 0x4E: /* LSR $nnnn */
LSR(6, ABSOLUTE, mem_write, addr);
break;
case 0x4F: /* SRE $nnnn */
SRE(6, ABSOLUTE, mem_write, addr);
break;
case 0x50: /* BVC $nnnn */
BVC();
break;
case 0x51: /* EOR ($nn),Y */
EOR(5, INDIR_Y_BYTE);
break;
case 0x53: /* SRE ($nn),Y */
SRE(8, INDIR_Y, mem_write, addr);
break;
case 0x55: /* EOR $nn,X */
EOR(4, ZP_IND_X_BYTE);
break;
case 0x56: /* LSR $nn,X */
LSR(6, ZP_IND_X, ZP_WRITE, baddr);
break;
case 0x57: /* SRE $nn,X */
SRE(6, ZP_IND_X, ZP_WRITE, baddr);
break;
case 0x58: /* CLI */
CLI();
break;
case 0x59: /* EOR $nnnn,Y */
EOR(4, ABS_IND_Y_BYTE);
break;
case 0x5B: /* SRE $nnnn,Y */
SRE(7, ABS_IND_Y, mem_write, addr);
break;
case 0x5D: /* EOR $nnnn,X */
EOR(4, ABS_IND_X_BYTE);
break;
case 0x5E: /* LSR $nnnn,X */
LSR(7, ABS_IND_X, mem_write, addr);
break;
case 0x5F: /* SRE $nnnn,X */
SRE(7, ABS_IND_X, mem_write, addr);
break;
case 0x60: /* RTS */
RTS();
break;
case 0x61: /* ADC ($nn,X) */
ADC(6, INDIR_X_BYTE);
break;
case 0x63: /* RRA ($nn,X) */
RRA(8, INDIR_X, mem_write, addr);
break;
case 0x65: /* ADC $nn */
ADC(3, ZERO_PAGE_BYTE);
break;
case 0x66: /* ROR $nn */
ROR(5, ZERO_PAGE, ZP_WRITE, baddr);
break;
case 0x67: /* RRA $nn */
RRA(5, ZERO_PAGE, ZP_WRITE, baddr);
break;
case 0x68: /* PLA */
PLA();
break;
case 0x69: /* ADC #$nn */
ADC(2, IMMEDIATE_BYTE);
break;
case 0x6A: /* ROR A */
ROR_A();
break;
case 0x6B: /* ARR #$nn */
ARR(2, IMMEDIATE_BYTE);
break;
case 0x6C: /* JMP ($nnnn) */
JMP_INDIRECT();
break;
case 0x6D: /* ADC $nnnn */
ADC(4, ABSOLUTE_BYTE);
break;
case 0x6E: /* ROR $nnnn */
ROR(6, ABSOLUTE, mem_write, addr);
break;
case 0x6F: /* RRA $nnnn */
RRA(6, ABSOLUTE, mem_write, addr);
break;
case 0x70: /* BVS $nnnn */
BVS();
break;
case 0x71: /* ADC ($nn),Y */
ADC(5, INDIR_Y_BYTE);
break;
case 0x73: /* RRA ($nn),Y */
RRA(8, INDIR_Y, mem_write, addr);
break;
case 0x75: /* ADC $nn,X */
ADC(4, ZP_IND_X_BYTE);
break;
case 0x76: /* ROR $nn,X */
ROR(6, ZP_IND_X, ZP_WRITE, baddr);
break;
case 0x77: /* RRA $nn,X */
RRA(6, ZP_IND_X, ZP_WRITE, baddr);
break;
case 0x78: /* SEI */
SEI();
break;
case 0x79: /* ADC $nnnn,Y */
ADC(4, ABS_IND_Y_BYTE);
break;
case 0x7B: /* RRA $nnnn,Y */
RRA(7, ABS_IND_Y, mem_write, addr);
break;
case 0x7D: /* ADC $nnnn,X */
ADC(4, ABS_IND_X_BYTE);
break;
case 0x7E: /* ROR $nnnn,X */
ROR(7, ABS_IND_X, mem_write, addr);
break;
case 0x7F: /* RRA $nnnn,X */
RRA(7, ABS_IND_X, mem_write, addr);
break;
case 0x80: /* NOP #$nn */
case 0x82: /* NOP #$nn */
case 0x89: /* NOP #$nn */
case 0xC2: /* NOP #$nn */
case 0xE2: /* NOP #$nn */
DOP(2);
break;
case 0x81: /* STA ($nn,X) */
STA(6, INDIR_X_ADDR, mem_write, addr);
break;
case 0x83: /* SAX ($nn,X) */
SAX(6, INDIR_X_ADDR, mem_write, addr);
break;
case 0x84: /* STY $nn */
STY(3, ZERO_PAGE_ADDR, ZP_WRITE, baddr);
break;
case 0x85: /* STA $nn */
STA(3, ZERO_PAGE_ADDR, ZP_WRITE, baddr);
break;
case 0x86: /* STX $nn */
STX(3, ZERO_PAGE_ADDR, ZP_WRITE, baddr);
break;
case 0x87: /* SAX $nn */
SAX(3, ZERO_PAGE_ADDR, ZP_WRITE, baddr);
break;
case 0x88: /* DEY */
DEY();
break;
case 0x8A: /* TXA */
TXA();
break;
case 0x8B: /* ANE #$nn */
ANE(2, IMMEDIATE_BYTE);
break;
case 0x8C: /* STY $nnnn */
STY(4, ABSOLUTE_ADDR, mem_write, addr);
break;
case 0x8D: /* STA $nnnn */
STA(4, ABSOLUTE_ADDR, mem_write, addr);
break;
case 0x8E: /* STX $nnnn */
STX(4, ABSOLUTE_ADDR, mem_write, addr);
break;
case 0x8F: /* SAX $nnnn */
SAX(4, ABSOLUTE_ADDR, mem_write, addr);
break;
case 0x90: /* BCC $nnnn */
BCC();
break;
case 0x91: /* STA ($nn),Y */
STA(6, INDIR_Y_ADDR, mem_write, addr);
break;
case 0x93: /* SHA ($nn),Y */
SHA(6, INDIR_Y_ADDR, mem_write, addr);
break;
case 0x94: /* STY $nn,X */
STY(4, ZP_IND_X_ADDR, ZP_WRITE, baddr);
break;
case 0x95: /* STA $nn,X */
STA(4, ZP_IND_X_ADDR, ZP_WRITE, baddr);
break;
case 0x96: /* STX $nn,Y */
STX(4, ZP_IND_Y_ADDR, ZP_WRITE, baddr);
break;
case 0x97: /* SAX $nn,Y */
SAX(4, ZP_IND_Y_ADDR, ZP_WRITE, baddr);
break;
case 0x98: /* TYA */
TYA();
break;
case 0x99: /* STA $nnnn,Y */
STA(5, ABS_IND_Y_ADDR, mem_write, addr);
break;
case 0x9A: /* TXS */
TXS();
break;
case 0x9B: /* SHS $nnnn,Y */
SHS(5, ABS_IND_Y_ADDR, mem_write, addr);
break;
case 0x9C: /* SHY $nnnn,X */
SHY(5, ABS_IND_X_ADDR, mem_write, addr);
break;
case 0x9D: /* STA $nnnn,X */
STA(5, ABS_IND_X_ADDR, mem_write, addr);
break;
case 0x9E: /* SHX $nnnn,Y */
SHX(5, ABS_IND_Y_ADDR, mem_write, addr);
break;
case 0x9F: /* SHA $nnnn,Y */
SHA(5, ABS_IND_Y_ADDR, mem_write, addr);
break;
case 0xA0: /* LDY #$nn */
LDY(2, IMMEDIATE_BYTE);
break;
case 0xA1: /* LDA ($nn,X) */
LDA(6, INDIR_X_BYTE);
break;
case 0xA2: /* LDX #$nn */
LDX(2, IMMEDIATE_BYTE);
break;
case 0xA3: /* LAX ($nn,X) */
LAX(6, INDIR_X_BYTE);
break;
case 0xA4: /* LDY $nn */
LDY(3, ZERO_PAGE_BYTE);
break;
case 0xA5: /* LDA $nn */
LDA(3, ZERO_PAGE_BYTE);
break;
case 0xA6: /* LDX $nn */
LDX(3, ZERO_PAGE_BYTE);
break;
case 0xA7: /* LAX $nn */
LAX(3, ZERO_PAGE_BYTE);
break;
case 0xA8: /* TAY */
TAY();
break;
case 0xA9: /* LDA #$nn */
LDA(2, IMMEDIATE_BYTE);
break;
case 0xAA: /* TAX */
TAX();
break;
case 0xAB: /* LXA #$nn */
LXA(2, IMMEDIATE_BYTE);
break;
case 0xAC: /* LDY $nnnn */
LDY(4, ABSOLUTE_BYTE);
break;
case 0xAD: /* LDA $nnnn */
LDA(4, ABSOLUTE_BYTE);
break;
case 0xAE: /* LDX $nnnn */
LDX(4, ABSOLUTE_BYTE);
break;
case 0xAF: /* LAX $nnnn */
LAX(4, ABSOLUTE_BYTE);
break;
case 0xB0: /* BCS $nnnn */
BCS();
break;
case 0xB1: /* LDA ($nn),Y */
LDA(5, INDIR_Y_BYTE);
break;
case 0xB3: /* LAX ($nn),Y */
LAX(5, INDIR_Y_BYTE);
break;
case 0xB4: /* LDY $nn,X */
LDY(4, ZP_IND_X_BYTE);
break;
case 0xB5: /* LDA $nn,X */
LDA(4, ZP_IND_X_BYTE);
break;
case 0xB6: /* LDX $nn,Y */
LDX(4, ZP_IND_Y_BYTE);
break;
case 0xB7: /* LAX $nn,Y */
LAX(4, ZP_IND_Y_BYTE);
break;
case 0xB8: /* CLV */
CLV();
break;
case 0xB9: /* LDA $nnnn,Y */
LDA(4, ABS_IND_Y_BYTE);
break;
case 0xBA: /* TSX */
TSX();
break;
case 0xBB: /* LAS $nnnn,Y */
LAS(4, ABS_IND_Y_BYTE);
break;
case 0xBC: /* LDY $nnnn,X */
LDY(4, ABS_IND_X_BYTE);
break;
case 0xBD: /* LDA $nnnn,X */
LDA(4, ABS_IND_X_BYTE);
break;
case 0xBE: /* LDX $nnnn,Y */
LDX(4, ABS_IND_Y_BYTE);
break;
case 0xBF: /* LAX $nnnn,Y */
LAX(4, ABS_IND_Y_BYTE);
break;
case 0xC0: /* CPY #$nn */
CPY(2, IMMEDIATE_BYTE);
break;
case 0xC1: /* CMP ($nn,X) */
CMP(6, INDIR_X_BYTE);
break;
case 0xC3: /* DCP ($nn,X) */
DCP(8, INDIR_X, mem_write, addr);
break;
case 0xC4: /* CPY $nn */
CPY(3, ZERO_PAGE_BYTE);
break;
case 0xC5: /* CMP $nn */
CMP(3, ZERO_PAGE_BYTE);
break;
case 0xC6: /* DEC $nn */
DEC(5, ZERO_PAGE, ZP_WRITE, baddr);
break;
case 0xC7: /* DCP $nn */
DCP(5, ZERO_PAGE, ZP_WRITE, baddr);
break;
case 0xC8: /* INY */
INY();
break;
case 0xC9: /* CMP #$nn */
CMP(2, IMMEDIATE_BYTE);
break;
case 0xCA: /* DEX */
DEX();
break;
case 0xCB: /* SBX #$nn */
SBX(2, IMMEDIATE_BYTE);
break;
case 0xCC: /* CPY $nnnn */
CPY(4, ABSOLUTE_BYTE);
break;
case 0xCD: /* CMP $nnnn */
CMP(4, ABSOLUTE_BYTE);
break;
case 0xCE: /* DEC $nnnn */
DEC(6, ABSOLUTE, mem_write, addr);
break;
case 0xCF: /* DCP $nnnn */
DCP(6, ABSOLUTE, mem_write, addr);
break;
case 0xD0: /* BNE $nnnn */
BNE();
break;
case 0xD1: /* CMP ($nn),Y */
CMP(5, INDIR_Y_BYTE);
break;
case 0xD3: /* DCP ($nn),Y */
DCP(8, INDIR_Y, mem_write, addr);
break;
case 0xD5: /* CMP $nn,X */
CMP(4, ZP_IND_X_BYTE);
break;
case 0xD6: /* DEC $nn,X */
DEC(6, ZP_IND_X, ZP_WRITE, baddr);
break;
case 0xD7: /* DCP $nn,X */
DCP(6, ZP_IND_X, ZP_WRITE, baddr);
break;
case 0xD8: /* CLD */
CLD();
break;
case 0xD9: /* CMP $nnnn,Y */
CMP(4, ABS_IND_Y_BYTE);
break;
case 0xDB: /* DCP $nnnn,Y */
DCP(7, ABS_IND_Y, mem_write, addr);
break;
case 0xDD: /* CMP $nnnn,X */
CMP(4, ABS_IND_X_BYTE);
break;
case 0xDE: /* DEC $nnnn,X */
DEC(7, ABS_IND_X, mem_write, addr);
break;
case 0xDF: /* DCP $nnnn,X */
DCP(7, ABS_IND_X, mem_write, addr);
break;
case 0xE0: /* CPX #$nn */
CPX(2, IMMEDIATE_BYTE);
break;
case 0xE1: /* SBC ($nn,X) */
SBC(6, INDIR_X_BYTE);
break;
case 0xE3: /* ISB ($nn,X) */
ISB(8, INDIR_X, mem_write, addr);
break;
case 0xE4: /* CPX $nn */
CPX(3, ZERO_PAGE_BYTE);
break;
case 0xE5: /* SBC $nn */
SBC(3, ZERO_PAGE_BYTE);
break;
case 0xE6: /* INC $nn */
INC(5, ZERO_PAGE, ZP_WRITE, baddr);
break;
case 0xE7: /* ISB $nn */
ISB(5, ZERO_PAGE, ZP_WRITE, baddr);
break;
case 0xE8: /* INX */
INX();
break;
case 0xE9: /* SBC #$nn */
case 0xEB: /* USBC #$nn */
SBC(2, IMMEDIATE_BYTE);
break;
case 0xEA: /* NOP */
NOP();
break;
case 0xEC: /* CPX $nnnn */
CPX(4, ABSOLUTE_BYTE);
break;
case 0xED: /* SBC $nnnn */
SBC(4, ABSOLUTE_BYTE);
break;
case 0xEE: /* INC $nnnn */
INC(6, ABSOLUTE, mem_write, addr);
break;
case 0xEF: /* ISB $nnnn */
ISB(6, ABSOLUTE, mem_write, addr);
break;
case 0xF0: /* BEQ $nnnn */
BEQ();
break;
case 0xF1: /* SBC ($nn),Y */
SBC(5, INDIR_Y_BYTE);
break;
case 0xF3: /* ISB ($nn),Y */
ISB(8, INDIR_Y, mem_write, addr);
break;
case 0xF5: /* SBC $nn,X */
SBC(4, ZP_IND_X_BYTE);
break;
case 0xF6: /* INC $nn,X */
INC(6, ZP_IND_X, ZP_WRITE, baddr);
break;
case 0xF7: /* ISB $nn,X */
ISB(6, ZP_IND_X, ZP_WRITE, baddr);
break;
case 0xF8: /* SED */
SED();
break;
case 0xF9: /* SBC $nnnn,Y */
SBC(4, ABS_IND_Y_BYTE);
break;
case 0xFB: /* ISB $nnnn,Y */
ISB(7, ABS_IND_Y, mem_write, addr);
break;
case 0xFD: /* SBC $nnnn,X */
SBC(4, ABS_IND_X_BYTE);
break;
case 0xFE: /* INC $nnnn,X */
INC(7, ABS_IND_X, mem_write, addr);
break;
case 0xFF: /* ISB $nnnn,X */
ISB(7, ABS_IND_X, mem_write, addr);
break;
}
/* Calculate remaining/elapsed clock cycles */
remaining_cycles -= instruction_cycles;
total_cycles += instruction_cycles;
}
_execute_done:
/* restore local copy of regs */
SET_LOCAL_REGS();
/* Return our actual amount of executed cycles */
return (total_cycles - old_cycles);
}
/* Initialize tables, etc. */
void nes6502_init(void)
{
int index;
/* Build the N / Z flag lookup table */
flag_table[0] = Z_FLAG;
for (index = 1; index < 256; index++)
flag_table[index] = (index & 0x80) ? N_FLAG : 0;
reg_A = reg_X = reg_Y = 0;
reg_S = 0xFF; /* Stack grows down */
}
/* Issue a CPU Reset */
void nes6502_reset(void)
{
reg_P = Z_FLAG | R_FLAG | I_FLAG; /* Reserved bit always 1 */
int_pending = dma_cycles = 0; /* No pending interrupts */
reg_PC = bank_readaddress(RESET_VECTOR); /* Fetch reset vector */
/* TODO: 6 cycles for RESET? */
}
/* Non-maskable interrupt */
void nes6502_nmi(void)
{
int_pending |= NMI_MASK;
}
/* Interrupt request */
void nes6502_irq(void)
{
int_pending |= IRQ_MASK;
}
/* Set dma period (in cycles) */
void nes6502_setdma(int cycles)
{
dma_cycles += cycles;
}
#ifdef NES6502_MEM_ACCESS_CTRL
void nes6502_chk_mem_access(uint8 * access, int flags)
{
chk_mem_access(access, flags);
}
#endif
/*
** $Log: nes6502.c,v $
** Revision 1.2 2003/05/01 22:34:19 benjihan
** New NSF plugin
**
** Revision 1.1 2003/04/08 20:53:00 ben
** Adding more files...
**
** Revision 1.6 2000/07/04 04:50:07 matt
** minor change to includes
**
** Revision 1.5 2000/07/03 02:18:16 matt
** added a few notes about potential failure cases
**
** Revision 1.4 2000/06/09 15:12:25 matt
** initial revision
**
*/