From: Frederik Schaffalitzky <fsm@ro...>  20020905 13:28:39

On Wed, 4 Sep 2002 Peter.Vanroose@... wrote: > Do you have a pointer to the documentation for this? No, only what I could find on the http://www. Correcting for endianness, the layout is always SEE...EEFF.....FF where S is the sign bit, E the exponent bits and F the mantissa ("fraction") bits. > Is the internal representation (and the division between mantissa and > exp) fixed once the total length of the representation is known? If > not, this has to be tested for in configure. Don't think so but these are the cases I have seen: single 1 + 8 + 23 = 32 double 1 + 11 + 52 = 64 doubleextended 1 + 15 + 64 = 80 quad 1 + 15 + 112 = 128 But I am no expert and I have not read the wonderful IEEE754 document. So far as I can see, the x86 80bit floating format ("long double" on my linux box) seems to not really be IEEE in that the leading "1" in the fraction part is included in the mantissa whereas in IEEE it is implied. Also, the "sizeof" size of my "long double" seems to be 12 bytes, with 16 bits of zeropadding on the left. With sparc/gcc it seems that "long double" is the quad IEEE type and takes 16 bytes. 