#15 Bad VCD scope output

open
nobody
None
5
2009-05-18
2009-05-18
Trevor Williams
No

I have several examples of VCD output scope definitions that lead to bad scopes with the latest version of Veriwell (2.8.7). Here's one example:

module main;

initial begin
#5;
call_task( 1'b0 );
end

initial begin
#10;
call_task( 1'b1 );
end

initial begin
`ifdef DUMP
$dumpfile( "task3.vcd" );
$dumpvars( 0, main );
`endif
#1000;
$finish;
end

task call_task;

input a;

begin
#100;
$display( $time, "Task called for a=%h", a );
end

endtask

endmodule

This generates the following VCD dumpfile:

$date
Sun May 17 23:47:15 2009

$end
$version
Veriwell 2.8.7
$end
$timescale
1s
$end

$scope task call_task $end
$var reg 1 ! a $end
$upscope $end

$upscope $end

$enddefinitions $end
#0
$dumpvars
x!
$end
#5
0!
#10
1!

The problem is that there is only one $scope call but two $upscope calls. There should be a $scope call for "main" prior to the $scope call to the "call_task" task. I have run into other issues where the $scope and $upscope calls don't match up (too many of one and not enough of the other). If this problem can be fixed, I can verify the other situations and append them to this bug report accordingly.

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