Version 1.2.1 was built and tested on Eclipse Luna SR2.
This release includes:
- Added some Verilog syntax checks.
From Sjors Hettinga:
- Ignoring encrypted Verilog code, based on the protected pragma.
- Using the used VHDL packages in a file, when jumping to a declaration of this value in a package.
- Upon VHDL detection of multiple implementations of the item you want to jump to.
- VHDL various syntax checks.... read more
Version 1.2.0 is here. As of this release, all official builds will use Java 7.
This release includes:
From Illian Dinev:
Added support for subtype definition jumping.
Improved code info hit popup
Autocomplete of "use" with common ieee libraries
New templates for record, array and subtype
From Maximilian Girlich:
Improved New File Template selection (for Verilog and VHDL)
Improved formatting in VHDL (alignment on => := and directional directives)
VEditor 1.2 is available via the testing update site. See the bottom of You can also put the main wiki page (sourceforge.net/apps/mediawiki/veditor/index.php?title=Main_Page) for information on how to get the latest testing version.
+ Better association of build errors with source files
+ Better handling of direct VHDL instantiations in the outline
+ Ability to use variables in the compile/simulate/build commands
The new version fixed some bugs and improved Verilog semantics checker.
The new version improves Verilog parser.
* Verilog syntax check more strictly.
* Add waring preference page.
* Add waring annotation about the followings:
"never used", "never assigned", "cannot be resolved", "assignment bit width mismatch" and "blocking and non-blocking assignment"
* Calculate parameter and localparam value in annotation hover.
It's time for another release of the VEditor. Even though, the version is reved to 1.0.0, this is a routine release. It will however, make future test releases easier by not wasting an extra digit. If the Linux kernel can do it, so can we :). Thanks to Stijn and Silvio for their contributions.
Here’s the list of bug fixes:
* Multi-line tabbing problem (ID 2726346)
* VHDL parser hangs (BUG ID 2952670)
* when using autocompletion, files often get mixed line endings
* mismatch between the classes RecordElement and TypeDecl, making autocompletion of record members to malfunction
* Fixed VHDL parser errors (3034727, and 1835772)... read more
The VEditor update and testing sites are operational again. See the Download section of the main page for details.
It's time for another version release. Bug fixes:
* When opening a very large VHDL file, the program may freeze or run out of memory.
* Type definitions did not show properly in the file outline.
Version 0.7.0 is released. Thanks to Stijn Last and his team for submitting most of the new features. Here's a list of what's new:
* Goto Definition now also searches in packages of other files, not only in current file.
* Solved few bugs, added alignment on :,=> and <= (e.g. if <= is present on multiple lines under each other this operator is aligned)
* Hoovering over the formal part of a component instatiation will now show the port's type.
* Implementation of Record member auto completion (when pressing "." after record instance name)
* Functionality to show matching parenthesis.
* Hoovering over a constant will show its value.
* Outline now also shows record declaration and members.
* Changed the way comments are added to signal declarations.
Now you have 2 options:... read more
Due to its multiple weaknesses, the wiki was constantly being hacked. Therefore, I have decided to revert back to the original html version of the web page.
Incorporated changes from Stijn Last. These improved the VHDL side of the house.
Here's the list of fixes/enhancements:
*The editor of Eclipse can be set to use spaces as tabs, the insertion of code templates and automatic component instantiations should be according to this setting
* Some altera generated files are encrypted. = binary file, but with .vhd extension. The internal VHDL parser gives on error on this.... read more
The VEditor wiki is back online again. Recently, Sourceforge revamped their entire ssh shell access and that caused our wiki to get very confused.
Also,nightly backups of the wiki are implemented. The backups are currently held on my computer and will facilitate the restoration of wiki data in case of future hacks/spam attacks.
You can download new veditor runtime and source package.
All the source code is now migrated to Subversion.
After experimenting and being very disappointed by the SourceForge.net wiki, I created our own MoinMoin based Wiki hosted on SourceForge.net. This wiki will also serve as the project's main webpage. You can find it at: http://veditor.sourceforge.net/
The VEditor Wiki is now operational! You should be able to access it from the main menu in the project page. Currently, the Wiki is a little a short on content but hopefully it will eventually serve as the central documentation for the project.
Eclipse Verilog editor is a plugin for the Eclipse IDE. It provides Verilog(IEEE-1364) and VHDL language specific code viewer, contents outline, code assist etc. It helps coding and debugging in hardware development based on Verilog or VHDL.
Eclipse VEditor 0.6.0 had been released. This release includes several new features such as:
* Complete VHDL parser
* Revamped File Outline
* Revamped Module Hierarchy
* Back-ground parser
* Document section collapsing
* VHDL comment continuation
* Multiple Build Configuration
* Error/Warning/Info Regex developer helper
* Improved VHDL auto-completion and Go-to-definition
* VHDL code formatter
* Other general usage improvements and code clean-ups.
The version 0.5.2 supports preference page for Verilog code formatter and fixes some bugs.
The version 0.5.1 adds block comment and uncomment command, and supports custom code template.
The version 0.5.0 changed license from GPL to EPL, and supported text hover of signals.
The version 4.1.0 has custom error parser and log viewer. It can support any Verilog/VHDL compilers.
The version 0.4.0 has Verilog/VHDL perspective, new module wizard and simulator builder in new Verilog/VHDL project. It supports Cver and FreeHDL compilers.
The version 0.3.2 supported Verilog 2001. It added generate/endgenerate template and instantiation with parameter.
The version 0.3.1 fixed some bugs.
The version 0.3.0 supported Code Formatter(beta) and Console view which shows external compiler messages and internal parser errors.
In addition, new version fixed some bugs.