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#74 Auto formatter incorrectly formats VHDL 'case' statements

open
nobody
None
5
2009-05-25
2009-05-25
Anonymous
No

Using the code below, when I select the whole code and then use 'Edit - Format',
the code indentation becomes incorrect on the 'end case' statement.
What happens, is that the line with 'case' and the line with 'end case' are indented to different levels.
This seems to happen to any 'case - when' statements.

--------------------------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity indentation_err is
port (
clk : in std_logic;
a, b, c : in std_logic;
d : out std_logic
);
end indentation_err;

architecture arch of indentation_err is

begin
process(clk) begin
if rising_edge(clk) then
case a is
when '0' => d <= b;
when '1' => d <= c;
when others => d <= '0';
end case;
end if;
end process;
end arch;

Discussion

  • Nobody/Anonymous

    The HDL file which gets formatted incorrectly

     
  • jhyoo

    jhyoo - 2009-05-26

    Found that this was resolved on the latest SVN version

     

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