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[Valgrind-developers] vex: r1248 - in trunk: . priv/guest-arm priv/guest-ppc32 priv/host-ppc32
|
From: <sv...@va...> - 2005-07-03 00:05:38
|
Author: sewardj
Date: 2005-07-03 01:05:31 +0100 (Sun, 03 Jul 2005)
New Revision: 1248
Log:
Type casting cleanups.
Modified:
trunk/Makefile-icc
trunk/priv/guest-arm/toIR.c
trunk/priv/guest-ppc32/ghelpers.c
trunk/priv/guest-ppc32/toIR.c
trunk/priv/host-ppc32/hdefs.c
trunk/priv/host-ppc32/isel.c
Modified: trunk/Makefile-icc
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/Makefile-icc 2005-07-02 19:24:10 UTC (rev 1247)
+++ trunk/Makefile-icc 2005-07-03 00:05:31 UTC (rev 1248)
@@ -19,6 +19,7 @@
priv/main/vex_globals.h \
priv/main/vex_util.h \
priv/guest-generic/g_generic_x87.h \
+ priv/guest-generic/bb_to_IR.h \
priv/guest-x86/gdefs.h \
priv/guest-amd64/gdefs.h \
priv/guest-arm/gdefs.h \
@@ -44,6 +45,7 @@
priv/host-generic/h_generic_simd64.o \
priv/host-generic/reg_alloc2.o \
priv/guest-generic/g_generic_x87.o \
+ priv/guest-generic/bb_to_IR.o \
priv/guest-x86/ghelpers.o \
priv/guest-amd64/ghelpers.o \
priv/guest-arm/ghelpers.o \
@@ -203,6 +205,10 @@
$(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/guest-generic/g_generic_x87.o =
\
-c priv/guest-generic/g_generic_x87.c
=20
+priv/guest-generic/bb_to_IR.o: $(ALL_HEADERS) priv/guest-generic/bb_to_I=
R.c
+ $(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/guest-generic/bb_to_IR.o \
+ -c priv/guest-generic/bb_to_IR.c
+
priv/guest-x86/ghelpers.o: $(ALL_HEADERS) priv/guest-x86/ghelpers.c
$(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/guest-x86/ghelpers.o \
-c priv/guest-x86/ghelpers.c
Modified: trunk/priv/guest-arm/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-arm/toIR.c 2005-07-02 19:24:10 UTC (rev 1247)
+++ trunk/priv/guest-arm/toIR.c 2005-07-03 00:05:31 UTC (rev 1248)
@@ -241,7 +241,7 @@
}
=20
delta +=3D size;
- vge->len[vge->n_used-1] +=3D size;
+ vge->len[vge->n_used-1] =3D toUShort(vge->len[vge->n_used-1] + siz=
e);
n_instrs++;
DIP("\n");
=20
Modified: trunk/priv/guest-ppc32/ghelpers.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/ghelpers.c 2005-07-02 19:24:10 UTC (rev 1247)
+++ trunk/priv/guest-ppc32/ghelpers.c 2005-07-03 00:05:31 UTC (rev 1248)
@@ -99,8 +99,8 @@
case PPC32G_FLAG_OP_MULLW: { // mullwo
/* OV true if result can't be represented in 32 bits
i.e sHi !=3D sign extension of sLo */
- Long l_res =3D (Long)((Int)argL) * (Long)((Int)argR);
- Int sHi =3D (Int)(l_res >> 32);
+ Long l_res =3D ((Long)((Int)argL)) * ((Long)((Int)argR));
+ Int sHi =3D (Int)toUInt(l_res >> 32);
Int sLo =3D (Int)l_res;
return (sHi !=3D (sLo >> /*s*/ 31)) ? 1:0;
}
Modified: trunk/priv/guest-ppc32/toIR.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/guest-ppc32/toIR.c 2005-07-02 19:24:10 UTC (rev 1247)
+++ trunk/priv/guest-ppc32/toIR.c 2005-07-03 00:05:31 UTC (rev 1248)
@@ -274,7 +274,7 @@
=20
static UChar extend_s_5to8 ( UChar x )
{
- return (UChar)((((Int)x) << 27) >> 27);
+ return toUChar((((Int)x) << 27) >> 27);
}
=20
#if 0
@@ -808,7 +808,7 @@
fld =3D getReg_masked( reg, (0xF << (field_idx*4)) );
=20
if (field_idx !=3D 0) {
- fld =3D binop(Iop_Shr32, fld, mkU8(field_idx * 4));
+ fld =3D binop(Iop_Shr32, fld, mkU8(toUChar(field_idx * 4)));
}
return fld;
}
@@ -818,13 +818,13 @@
static IRExpr* getReg_bit ( PPC32SPR reg, UInt bit_idx )
{
IRExpr* val;
- vassert( bit_idx <=3D 32 );
+ vassert( bit_idx < 32 );
vassert( reg < PPC32_SPR_MAX );
=20
val =3D getReg_masked( reg, 1<<bit_idx );
=20
if (bit_idx !=3D 0) {
- val =3D binop(Iop_Shr32, val, mkU8(bit_idx));
+ val =3D binop(Iop_Shr32, val, mkU8(toUChar(bit_idx)));
}
return val;
}
@@ -955,7 +955,7 @@
vassert( reg < PPC32_SPR_MAX );
=20
if (field_idx !=3D 0) {
- src =3D binop(Iop_Shl32, src, mkU8(field_idx * 4));
+ src =3D binop(Iop_Shl32, src, mkU8(toUChar(field_idx * 4)));
} =20
putReg_masked( reg, src, (0xF << (field_idx*4)) );
}
@@ -968,18 +968,12 @@
vassert( reg < PPC32_SPR_MAX );
=20
if (bit_idx !=3D 0) {
- src =3D binop(Iop_Shl32, src, mkU8(bit_idx));
+ src =3D binop(Iop_Shl32, src, mkU8(toUChar(bit_idx)));
} =20
putReg_masked( reg, src, (1<<bit_idx) );
}
=20
=20
-
-
-
-
-
-
/*------------------------------------------------------------*/
/*--- Integer Instruction Translation --- */
/*------------------------------------------------------------*/
@@ -1370,13 +1364,13 @@
switch (opc1) {
case 0x0B: // cmpi (Compare Immediate, PPC32 p368)
EXTS_SIMM =3D extend_s_16to32(SIMM_16);
- DIP("cmpi crf%d,%u,r%d,0x%x\n", crfD, flag_L, Ra_addr, EXTS_SIMM);
+ DIP("cmpi crf%d,%d,r%d,0x%x\n", crfD, flag_L, Ra_addr, EXTS_SIMM);
irx_cmp_lt =3D binop(Iop_CmpLT32S, mkexpr(Ra), mkU32(EXTS_SIMM));
irx_cmp_eq =3D binop(Iop_CmpEQ32, mkexpr(Ra), mkU32(EXTS_SIMM));
break;
=20
case 0x0A: // cmpli (Compare Logical Immediate, PPC32 p370)
- DIP("cmpli crf%d,%u,r%d,0x%x\n", crfD, flag_L, Ra_addr, UIMM_16);
+ DIP("cmpli crf%d,%d,r%d,0x%x\n", crfD, flag_L, Ra_addr, UIMM_16);
irx_cmp_lt =3D binop(Iop_CmpLT32U, mkexpr(Ra), mkU32(UIMM_16));
irx_cmp_eq =3D binop(Iop_CmpEQ32, mkexpr(Ra), mkU32(UIMM_16));
break;
@@ -1392,13 +1386,13 @@
=20
switch (opc2) {
case 0x000: // cmp (Compare, PPC32 p367)
- DIP("cmp crf%d,%u,r%d,r%d\n", crfD, flag_L,
+ DIP("cmp crf%d,%d,r%d,r%d\n", crfD, flag_L,
Ra_addr, Rb_addr);
irx_cmp_lt =3D binop(Iop_CmpLT32S, mkexpr(Ra), mkexpr(Rb));
break;
=20
case 0x020: // cmpl (Compare Logical, PPC32 p369)
- DIP("cmpl crf%d,%u,r%d,r%d\n", crfD, flag_L,
+ DIP("cmpl crf%d,%d,r%d,r%d\n", crfD, flag_L,
Ra_addr, Rb_addr);
irx_cmp_lt =3D binop(Iop_CmpLT32U, mkexpr(Ra), mkexpr(Rb));
break;
@@ -1642,7 +1636,7 @@
=20
switch (opc1) {
case 0x14: // rlwimi (Rotate Left Word Immediate then Mask Insert, PP=
C32 p500)
- DIP("rlwimi%s r%d,r%d,%d,%u,%u\n", flag_Rc ? "." : "",
+ DIP("rlwimi%s r%d,r%d,%d,%d,%d\n", flag_Rc ? "." : "",
Ra_addr, Rs_addr, sh_imm, MaskBegin, MaskEnd);
// Ra =3D (ROTL(Rs, Imm) & mask) | (Ra & ~mask);
assign( Ra, binop(Iop_Or32,
@@ -1652,7 +1646,7 @@
break;
=20
case 0x15: // rlwinm (Rotate Left Word Immediate then AND with Mask, =
PPC32 p501)
- DIP("rlwinm%s r%d,r%d,%d,%u,%u\n", flag_Rc ? "." : "",
+ DIP("rlwinm%s r%d,r%d,%d,%d,%d\n", flag_Rc ? "." : "",
Ra_addr, Rs_addr, sh_imm, MaskBegin, MaskEnd);
// Ra =3D ROTL(Rs, Imm) & mask
assign( Ra, binop(Iop_And32, ROTL32(mkexpr(Rs),
@@ -1660,7 +1654,7 @@
break;
=20
case 0x17: // rlwnm (Rotate Left Word then AND with Mask, PPC32 p503
- DIP("rlwnm%s r%d,r%d,r%d,%u,%u\n", flag_Rc ? "." : "",
+ DIP("rlwnm%s r%d,r%d,r%d,%d,%d\n", flag_Rc ? "." : "",
Ra_addr, Rs_addr, Rb_addr, MaskBegin, MaskEnd);
// Ra =3D ROTL(Rs, Rb[0-4]) & mask
assign( rot_amt,
@@ -2147,7 +2141,7 @@
return False;
}
}
- DIP("lswi r%d,r%d,%u\n", Rd_addr, Ra_addr, NumBytes);
+ DIP("lswi r%d,r%d,%d\n", Rd_addr, Ra_addr, NumBytes);
=20
assign( EA, mkexpr(b_EA) );
=20
@@ -2182,7 +2176,7 @@
case 0x2D5: // stswi (Store String Word Immediate, PPC32 p528)
vassert(0);
=20
- DIP("stswi r%d,r%d,%u\n", Rs_addr, Ra_addr, NumBytes);
+ DIP("stswi r%d,r%d,%d\n", Rs_addr, Ra_addr, NumBytes);
if (Ra_addr =3D=3D 0) {
assign( EA, mkU32(0) );
} else {
@@ -3286,7 +3280,7 @@
/* D-Form */
UInt d_imm =3D (theInstr >> 0) & 0xFFFF; /* theInstr[0:=
15] */
=20
- UInt exts_d_imm =3D extend_s_16to32(d_imm);
+ Int exts_d_imm =3D extend_s_16to32(d_imm);
=20
IRTemp EA =3D newTemp(Ity_I32);
IRTemp rA =3D newTemp(Ity_I32);
@@ -3299,7 +3293,7 @@
=20
switch(opc1) {
case 0x30: // lfs (Load Float Single, PPC32 p441)
- DIP("lfs fr%d,%d(r%d)\n", frD_addr, d_imm, rA_addr);
+ DIP("lfs fr%d,%d(r%d)\n", frD_addr, exts_d_imm, rA_addr);
assign( EA, binop(Iop_Add32, mkU32(exts_d_imm), mkexpr(rA_or_0)) )=
;
putFReg( frD_addr, unop(Iop_F32toF64, loadBE(Ity_F32, mkexpr(EA)))=
);
break;
@@ -3309,14 +3303,14 @@
vex_printf("dis_fp_load(PPC32)(instr,lfsu)\n");
return False;
}
- DIP("lfsu fr%d,%d(r%d)\n", frD_addr, d_imm, rA_addr);
+ DIP("lfsu fr%d,%d(r%d)\n", frD_addr, exts_d_imm, rA_addr);
assign( EA, binop(Iop_Add32, mkU32(exts_d_imm), mkexpr(rA)) );
putFReg( frD_addr, unop(Iop_F32toF64, loadBE(Ity_F32, mkexpr(EA)))=
);
putIReg( rA_addr, mkexpr(EA) );
break;
=20
case 0x32: // lfd (Load Float Double, PPC32 p437)
- DIP("lfd fr%d,%d(r%d)\n", frD_addr, d_imm, rA_addr);
+ DIP("lfd fr%d,%d(r%d)\n", frD_addr, exts_d_imm, rA_addr);
assign( EA, binop(Iop_Add32, mkU32(exts_d_imm), mkexpr(rA_or_0)) )=
;
putFReg( frD_addr, loadBE(Ity_F64, mkexpr(EA)) );
break;
@@ -3326,7 +3320,7 @@
vex_printf("dis_fp_load(PPC32)(instr,lfdu)\n");
return False;
}
- DIP("lfdu fr%d,%d(r%d)\n", frD_addr, d_imm, rA_addr);
+ DIP("lfdu fr%d,%d(r%d)\n", frD_addr, exts_d_imm, rA_addr);
assign( EA, binop(Iop_Add32, mkU32(exts_d_imm), mkexpr(rA)) );
putFReg( frD_addr, loadBE(Ity_F64, mkexpr(EA)) );
putIReg( rA_addr, mkexpr(EA) );
@@ -3404,7 +3398,7 @@
/* D-Form */
UInt d_imm =3D (theInstr >> 0) & 0xFFFF; /* theInstr[0:=
15] */
=20
- UInt exts_d_imm =3D extend_s_16to32(d_imm);
+ Int exts_d_imm =3D extend_s_16to32(d_imm);
=20
IRTemp EA =3D newTemp(Ity_I32);
IRTemp frS =3D newTemp(Ity_F64);
@@ -3419,7 +3413,7 @@
=20
switch(opc1) {
case 0x34: // stfs (Store Float Single, PPC32 p518)
- DIP("stfs fr%d,%d(r%d)\n", frS_addr, d_imm, rA_addr);
+ DIP("stfs fr%d,%d(r%d)\n", frS_addr, exts_d_imm, rA_addr);
assign( EA, binop(Iop_Add32, mkU32(exts_d_imm), mkexpr(rA_or_0)) )=
;
storeBE( mkexpr(EA),
binop(Iop_F64toF32, get_roundingmode(), mkexpr(frS)) );
@@ -3430,7 +3424,7 @@
vex_printf("dis_fp_store(PPC32)(instr,stfsu)\n");
return False;
}
- DIP("stfsu fr%d,%d(r%d)\n", frS_addr, d_imm, rA_addr);
+ DIP("stfsu fr%d,%d(r%d)\n", frS_addr, exts_d_imm, rA_addr);
assign( EA, binop(Iop_Add32, mkU32(exts_d_imm), mkexpr(rA)) );
storeBE( mkexpr(EA),
binop(Iop_F64toF32, get_roundingmode(), mkexpr(frS)) );
@@ -3438,7 +3432,7 @@
break;
=20
case 0x36: // stfd (Store Float Double, PPC32 p513)
- DIP("stfd fr%d,%d(r%d)\n", frS_addr, d_imm, rA_addr);
+ DIP("stfd fr%d,%d(r%d)\n", frS_addr, exts_d_imm, rA_addr);
assign( EA, binop(Iop_Add32, mkU32(exts_d_imm), mkexpr(rA_or_0)) )=
;
storeBE( mkexpr(EA), mkexpr(frS) );
break;
@@ -3448,7 +3442,7 @@
vex_printf("dis_fp_store(PPC32)(instr,stfdu)\n");
return False;
}
- DIP("stfdu fr%d,%d(r%d)\n", frS_addr, d_imm, rA_addr);
+ DIP("stfdu fr%d,%d(r%d)\n", frS_addr, exts_d_imm, rA_addr);
assign( EA, binop(Iop_Add32, mkU32(exts_d_imm), mkexpr(rA)) );
storeBE( mkexpr(EA), mkexpr(frS) );
putIReg( rA_addr, mkexpr(EA) );
@@ -5046,7 +5040,7 @@
vex_printf("dis_av_permute(PPC32)(vsldoi)\n");
return False;
}
- DIP("vsldoi v%d,v%d,v%d,%u\n", vD_addr, vA_addr, vB_addr, SHB_uimm=
4);
+ DIP("vsldoi v%d,v%d,v%d,%d\n", vD_addr, vA_addr, vB_addr, SHB_uimm=
4);
DIP(" =3D> not implemented\n");
return False;
=20
@@ -5090,17 +5084,17 @@
=20
/* Splat */
case 0x20C: // vspltb (Splat Byte, AV p245)
- DIP("vspltb v%d,v%d,%u\n", vD_addr, vB_addr, UIMM_5);
+ DIP("vspltb v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5);
DIP(" =3D> not implemented\n");
return False;
=20
case 0x24C: // vsplth (Splat Half Word, AV p246)
- DIP("vsplth v%d,v%d,%u\n", vD_addr, vB_addr, UIMM_5);
+ DIP("vsplth v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5);
DIP(" =3D> not implemented\n");
return False;
=20
case 0x28C: // vspltw (Splat Word, AV p250)
- DIP("vspltw v%d,v%d,%u\n", vD_addr, vB_addr, UIMM_5);
+ DIP("vspltw v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5);
DIP(" =3D> not implemented\n");
return False;
=20
@@ -5395,22 +5389,22 @@
=20
switch (opc2) {
case 0x30A: // vcfux (Convert from Unsigned Fixed-Point W, AV p156)
- DIP("vcfux v%d,v%d,%u\n", vD_addr, vB_addr, UIMM_5);
+ DIP("vcfux v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5);
DIP(" =3D> not implemented\n");
return False;
=20
case 0x34A: // vcfsx (Convert from Signed Fixed-Point W, AV p155)
- DIP("vcfsx v%d,v%d,%u\n", vD_addr, vB_addr, UIMM_5);
+ DIP("vcfsx v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5);
DIP(" =3D> not implemented\n");
return False;
=20
case 0x38A: // vctuxs (Convert to Unsigned Fixed-Point W Saturate, AV=
p172)
- DIP("vctuxs v%d,v%d,%u\n", vD_addr, vB_addr, UIMM_5);
+ DIP("vctuxs v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5);
DIP(" =3D> not implemented\n");
return False;
=20
case 0x3CA: // vctsxs (Convert to Signed Fixed-Point W Saturate, AV p=
171)
- DIP("vctsxs v%d,v%d,%u\n", vD_addr, vB_addr, UIMM_5);
+ DIP("vctsxs v%d,v%d,%d\n", vD_addr, vB_addr, UIMM_5);
DIP(" =3D> not implemented\n");
return False;
=20
Modified: trunk/priv/host-ppc32/hdefs.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/hdefs.c 2005-07-02 19:24:10 UTC (rev 1247)
+++ trunk/priv/host-ppc32/hdefs.c 2005-07-03 00:05:31 UTC (rev 1248)
@@ -1321,12 +1321,14 @@
ppHRegPPC32(i->Pin.AvShlDbl.srcL);
vex_printf(",");
ppHRegPPC32(i->Pin.AvShlDbl.srcR);
- vex_printf(",%u", i->Pin.AvShlDbl.shift);
+ vex_printf(",%d", i->Pin.AvShlDbl.shift);
return;
=20
case Pin_AvSplat: {
- UChar ch_sz =3D (i->Pin.AvSplat.sz =3D=3D 8) ? 'b' :
- (i->Pin.AvSplat.sz =3D=3D 16) ? 'h' : 'w';
+ UChar ch_sz =3D toUChar(
+ (i->Pin.AvSplat.sz =3D=3D 8) ? 'b' :
+ (i->Pin.AvSplat.sz =3D=3D 16) ? 'h' : 'w'
+ );
vex_printf("vsplt%s%c ",
i->Pin.AvSplat.src->tag =3D=3D Pri_Imm ? "is" : "", ch_=
sz);
ppHRegPPC32(i->Pin.AvSplat.dst);
Modified: trunk/priv/host-ppc32/isel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- trunk/priv/host-ppc32/isel.c 2005-07-02 19:24:10 UTC (rev 1247)
+++ trunk/priv/host-ppc32/isel.c 2005-07-03 00:05:31 UTC (rev 1248)
@@ -706,7 +706,7 @@
=20
/* Finally, the call itself. */
addInstr(env, PPC32Instr_Call( cc,
- Ptr_to_ULong(cee->addr),
+ (Addr32)toUInt(Ptr_to_ULong(cee->addr)=
),
n_args + (passBBP ? 1 : 0) ));
}
=20
@@ -915,8 +915,8 @@
if (e->Iex.Load.end !=3D Iend_BE)
goto irreducible;
if (ty =3D=3D Ity_I8 || ty =3D=3D Ity_I16 || ty =3D=3D Ity_I32) {
- addInstr(env, PPC32Instr_Load(=20
- sizeofIRType(ty), False, r_dst, am_addr ));
+ addInstr(env, PPC32Instr_Load( toUChar(sizeofIRType(ty)),=20
+ False, r_dst, am_addr ));
return r_dst;
}
break;
@@ -1385,7 +1385,8 @@
if (ty =3D=3D Ity_I8 || ty =3D=3D Ity_I16 || ty =3D=3D Ity_I32) {
HReg r_dst =3D newVRegI(env);
PPC32AMode* am_addr =3D PPC32AMode_IR(e->Iex.Get.offset, GuestS=
tatePtr );
- addInstr(env, PPC32Instr_Load( sizeofIRType(ty), False, r_dst, =
am_addr ));
+ addInstr(env, PPC32Instr_Load( toUChar(sizeofIRType(ty)),=20
+ False, r_dst, am_addr ));
return r_dst;
}
break;
@@ -1477,21 +1478,25 @@
Int i =3D u & 0xFFFF;
i <<=3D 16;
i >>=3D 16;
- return u =3D=3D (UInt)i;
+ return toBool(u =3D=3D (UInt)i);
}
=20
static Bool sane_AMode ( PPC32AMode* am )
{
switch (am->tag) {
case Pam_IR:
- return (hregClass(am->Pam.IR.base) =3D=3D HRcInt32
- && hregIsVirtual(am->Pam.IR.base)
- && fits16bits(am->Pam.IR.index));
+ return toBool(
+ hregClass(am->Pam.IR.base) =3D=3D HRcInt32
+ && hregIsVirtual(am->Pam.IR.base)
+ && fits16bits(am->Pam.IR.index)
+ );
case Pam_RR:
- return (hregClass(am->Pam.RR.base) =3D=3D HRcInt32
- && hregIsVirtual(am->Pam.IR.base)
- && hregClass(am->Pam.RR.base) =3D=3D HRcInt32
- && hregIsVirtual(am->Pam.IR.base));
+ return toBool(
+ hregClass(am->Pam.RR.base) =3D=3D HRcInt32
+ && hregIsVirtual(am->Pam.IR.base)
+ && hregClass(am->Pam.RR.base) =3D=3D HRcInt32
+ && hregIsVirtual(am->Pam.IR.base)
+ );
default:
vpanic("sane_AMode: unknown ppc32 amode tag");
}
@@ -1939,7 +1944,7 @@
which. */
HReg tLo =3D newVRegI(env);
HReg tHi =3D newVRegI(env);
- Bool syned =3D e->Iex.Binop.op =3D=3D Iop_MullS32;
+ Bool syned =3D toBool(e->Iex.Binop.op =3D=3D Iop_MullS32)=
;
HReg r_srcL =3D iselIntExpr_R(env, e->Iex.Binop.arg1);
=20
// CAB: could do better than this...
@@ -2468,7 +2473,7 @@
//.. return;
//.. }
=20
- vex_printf("iselInt64Expr(ppc32): No such tag(%d)\n", e->tag);
+ vex_printf("iselInt64Expr(ppc32): No such tag(%u)\n", e->tag);
ppIRExpr(e);
vpanic("iselInt64Expr(ppc32)");
}
@@ -2546,7 +2551,7 @@
//.. return dst;
//.. }
=20
- vex_printf("iselFltExpr(ppc32): No such tag(%d)\n", e->tag);
+ vex_printf("iselFltExpr(ppc32): No such tag(%u)\n", e->tag);
ppIRExpr(e);
vpanic("iselFltExpr_wrk(ppc32)");
}
@@ -2783,7 +2788,7 @@
}
}
=20
- vex_printf("iselDblExpr(ppc32): No such tag(%d)\n", e->tag);
+ vex_printf("iselDblExpr(ppc32): No such tag(%u)\n", e->tag);
ppIRExpr(e);
vpanic("iselDblExpr_wrk(ppc32)");
}
@@ -3301,7 +3306,8 @@
am_addr =3D iselIntExpr_AMode(env, stmt->Ist.Store.addr);
if (tyd =3D=3D Ity_I8 || tyd =3D=3D Ity_I16 || tyd =3D=3D Ity_I32)=
{
HReg r_src =3D iselIntExpr_R(env, stmt->Ist.Store.data);
- addInstr(env, PPC32Instr_Store(sizeofIRType(tyd), am_addr, r_sr=
c));
+ addInstr(env, PPC32Instr_Store( toUChar(sizeofIRType(tyd)),=20
+ am_addr, r_src));
return;
}
if (tyd =3D=3D Ity_F64) {
@@ -3338,7 +3344,8 @@
if (ty =3D=3D Ity_I8 || ty =3D=3D Ity_I16 || ty =3D=3D Ity_I32) {
HReg r_src =3D iselIntExpr_R(env, stmt->Ist.Put.data);
PPC32AMode* am_addr =3D PPC32AMode_IR(stmt->Ist.Put.offset, Gue=
stStatePtr);
- addInstr(env, PPC32Instr_Store( sizeofIRType(ty), am_addr, r_sr=
c ));
+ addInstr(env, PPC32Instr_Store( toUChar(sizeofIRType(ty)),=20
+ am_addr, r_src ));
return;
}
if (ty =3D=3D Ity_I64) {
@@ -3454,7 +3461,7 @@
=20
if (d->nFxState =3D=3D 0)
vassert(!d->needsBBP);
- passBBP =3D d->nFxState > 0 && d->needsBBP;
+ passBBP =3D toBool(d->nFxState > 0 && d->needsBBP);
=20
/* Marshal args, do the call, clear stack. */
doHelperCall( env, passBBP, d->guard, d->cee, d->args );
|