SystemVerilog simulations can have randomization-stability issues. At least the following are known causes:
1) "import" statements into global namespace (i.e. outside of package/module/interface)
2) $random (use $urandom instead)
It would be very useful if SVE were able to detect these, especially #1, as it requires a complete parser (one could have a `include which has a 'import' statement in it).