#63 Add option to work as defined-type langunge?

open
nobody
None
5
2013-03-22
2013-03-22
Maurice Ravel
No

One thing I hate in Verilog HDL is implicit declaration.

I havn't found any merit of implicit declaration yet, however it sent me Hell several times.

I tried use `default_nettype none compiler derivative.
However it required to me change all 'input' to 'input wire'.
I could tell my colleague to add declarations to all wires, but I failed to change 'input' to 'input wire'. Acutally, it was very difficult to me.

Could add option to be a mimic of defined-type language in SVEditor?

I want to restrict me by below rules.

  • Only input and output keywords can declare implicitly wire (or default_nettype).
  • Re-defining of any veriable is illegal (It may be difficult to restrict because Verilog HDL allows writing 'output reg' into two lines...)
  • Do not allow same name module in one project (or a world managed by argument file)

Related

Feature Requests: #63

Discussion

  • Erik Jessen
    Erik Jessen
    2013-03-22

    Maurice,
    I like these - I'm working to get SVE to be able to do a bit of linting as well (like bus-width mismatches, type mismatches).

    And these are also good items. I've hit them as well.

    Given that some people will not want to see any messages like this, it would probably be best to have a 'lint' page under preferences, where users can turn them on/off.
    And have some way to enable/disable in an argument file, that can be specified on cmdline, or in project preferences.

    From: Maurice Ravel [mailto:mauriceravel@users.sf.net]
    Sent: Friday, March 22, 2013 7:40 AM
    To: Ticket 63
    Subject: [sveditor:feature-requests] #63 Add option to work as defined-type langunge?


    [feature-requests:#63]http://sourceforge.net/p/sveditor/feature-requests/63/ Add option to work as defined-type langunge?

    Status: open
    Created: Fri Mar 22, 2013 02:39 PM UTC by Maurice Ravel
    Last Updated: Fri Mar 22, 2013 02:39 PM UTC
    Owner: nobody

    One thing I hate in Verilog HDL is implicit declaration.

    I havn't found any merit of implicit declaration yet, however it sent me Hell several times.

    I tried use `default_nettype none compiler derivative.
    However it required to me change all 'input' to 'input wire'.
    I could tell my colleague to add declarations to all wires, but I failed to change 'input' to 'input wire'. Acutally, it was very difficult to me.

    Could add option to be a mimic of defined-type language in SVEditor?

    I want to restrict me by below rules.

    • Only input and output keywords can declare implicitly wire (or default_nettype).
    • Re-defining of any veriable is illegal (It may be difficult to restrict because Verilog HDL allows writing 'output reg' into two lines...)
    • Do not allow same name module in one project (or a world managed by argument file)

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    Related

    Feature Requests: #63